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AMD Announces the Radeon Instinct Family of Deep-Learning Accelerators

AMD (NASDAQ: AMD) today unveiled its strategy to accelerate the machine intelligence era in server computing through a new suite of hardware
and open-source software offerings designed to dramatically increase performance, efficiency, and ease of implementation of deep learning workloads. New Radeon Instinct accelerators will offer organizations powerful GPU-based solutions for deep learning inference and training. Along with the new hardware offerings, AMD announced MIOpen, a free, open-source library for GPU accelerators intended to enable high-performance machine intelligence implementations, and new, optimized deep learning frameworks on AMD's ROCm software to build the foundation of the next evolution of machine intelligence workloads.

Inexpensive high-capacity storage, an abundance of sensor driven data, and the exponential growth of user-generated content are driving exabytes of data globally. Recent advances in machine intelligence algorithms mapped to high-performance GPUs are enabling orders of magnitude acceleration of the processing and understanding of that data, producing insights in near real time. Radeon Instinct is a blueprint for an open software ecosystem for machine intelligence, helping to speed inference insights and algorithm training.

Industry Leaders Join Forces to Promote New High-Performance Interconnect

A group of leading technology companies today announced the Gen-Z Consortium, an industry alliance working to create and commercialize a new scalable computing interconnect and protocol. This flexible, high-performance memory semantic fabric provides a peer-to-peer interconnect that easily accesses large volumes of data while lowering costs and avoiding today's bottlenecks. The alliance members include AMD, ARM, Cavium Inc., Cray, Dell EMC, Hewlett Packard Enterprise (HPE), Huawei, IBM, IDT, Lenovo, Mellanox Technologies, Micron, Microsemi, Red Hat, Samsung, Seagate, SK hynix, Western Digital Corporation, and Xilinx.

Modern computer systems have been built around the assumption that storage is slow, persistent and reliable, while data in memory is fast but volatile. As new storage class memory technologies emerge that drive the convergence of storage and memory attributes, the programmatic and architectural assumptions that have worked in the past are no longer optimal. The challenges associated with explosive data growth, real-time application demands, the emergence of low latency storage class memory, and demand for rack scale resource pools require a new approach to data access.

Seagate Announces New Alignment of Global Markets & Customers Organization

Seagate Technology plc (NASDAQ: STX), a world leader in storage solutions, today announced that its Global Markets & Customers organization will be aligned under Dave Mosley, President, Operations and Technology, effective immediately. Mr. Mosley will continue to report to Steve Luczo, Chairman and Chief Executive Officer.

"I'm looking forward to working with Dave over the next several years as we continue to optimize Seagate in a way to best serve our expanding global customer base. Seagate's focus on operational efficiency in our global high technology manufacturing facilities and design centers has benefitted our storage technology portfolio, competitive position and financial performance," said Mr. Luczo. "Given these positive results, we are extending this operational efficiency into Seagate's market-facing functions to help further align our structure. We expect the transition to be seamless, as Dave has previously managed Seagate's sales, marketing and product management functions."

Rocky Pimentel, Seagate's President of Global Markets and Customers will remain with the company as Executive Vice President and report to Mr. Luczo. Mr. Pimentel will have responsibility for a number of strategic projects within the company and will continue to serve on selected boards.

TSMC 16FinFET Plus Process Achieves Risk Production Milestone

TSMC today announced its 16-nanometer FinFET Plus (16FF+) process is now in risk production. This enhanced version of TSMC's 16FF process operates 40% faster than the company's planar 20-nanometer system-on-chip (20SoC) process, or consumes 50% less power at the same speed. It offers customers a new level of performance and power optimization targeted at the next generation of high-end mobile, computing, networking, and consumer applications.

TSMC's 16nm process offers an extended scaling of advanced SoC designs and is verified to reach speeds of 2.3GHz with ARM's "big" Cortex-A57 in high-speed applications while consuming as little as 75mW with the "LITTLE" Cortex-A53 in low-power applications. It is making excellent progress in yield learning, and has achieved the best technology maturity at the same corresponding stage as compared to all TSMC's previous nodes.

Hybrid Memory Cube Consortium Finalizes Specifications

More than 100 developer and adopter members of the Hybrid Memory Cube Consortium (HMCC) today announced they've reached consensus for the global standard that will deliver a much-anticipated, disruptive memory computing solution. Developed in only 17 months, the final specification marks the turning point for designers in a wide range of segments-from networking and high-performance computing, to industrial and beyond-to begin designing Hybrid Memory Cube (HMC) technology into future products.

A major breakthrough with HMC is the long-awaited utilization of advanced technologies to combine highperformance logic with state-of-the-art DRAM. With this first HMC milestone reached so quickly, consortium members have elected to extend their collaborative effort to achieve agreement on the next generation of HMC interface standards.

Xilinx 7 Series FPGA/Micron RLDRAM 3 Platform Enables Substantially Higher Data Rates

Xilinx, Inc. and Micron Technology, Inc., today announced the first public hardware demonstration of an FPGA interfacing with RLDRAM 3 memory, a new and emerging memory standard for high-end networking applications such as packet buffering and inspection, linked lists, and lookup tables. Operating with Virtex-7 and Kintex-7 FPGAs at data rates up to 1600 megabits per second (Mb/s), Micron's high-performance RLDRAM 3 memory combines high density, high bandwidth and fast SRAM-like random access to enable a 60 percent higher data rate and memory bandwidth compared to that of the previous generation (Virtex-6 FPGAs/RLDRAM2 memory standard). RLDRAM 3 memory enables 40G and 100G networking systems that require higher speed, higher density, lower power and lower latency.

Virtex-7 and Kintex-7 FPGAs are designed with the necessary IO standards and architectural components for optimal interfacing with RLDRAM 3, providing a significant boost to system performance for high-performance wireless and wired networking systems. RLDRAM 3 memory uses innovative circuit design to minimize the time between the beginning of an access cycle and the instant that the first data is available. Ultra-low bus turnaround time enables higher sustainable bandwidth with near-term balanced read-to-write ratios.
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