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AMD Zen3 to Leverage 7nm+ EUV For 20% Transistor Density Increase

AMD "Zen 3" microarchitecture could be designed for the enhanced 7 nm+ EUV (extreme ultraviolet) silicon fabrication node at TSMC, which promises a significant 20 percent increase in transistor densities compared to the 7 nm DUV (deep ultraviolet) node on which its "Zen 2" processors are being built. In addition, the node will also reduce power consumption by up to 10 percent at the same operational load. In a late-2018 interview, CTO Mark Papermaster stated AMD's design goal with "Zen 3" would be to prioritize energy-efficiency, and that it would present "modest" performance improvements (read: IPC improvements) over "Zen 2." AMD made it clear that it won't drag 7 nm DUV over more than one microarchitecture (Zen 2), and that "Zen 3" will debut in 2020 on 7 nm+ EUV.

MSI Betrays AMD's Socket AM4 Longevity Promise: No Zen2 for 300-series?

Greedy motherboard vendors such as MSI want you to buy a new motherboard every two generations of processor for no sound reason at all. MSI is reportedly blocking support for 3rd generation Ryzen "Matisse" processors on its AMD 300-series chipset motherboards, including those based on high-end AMD X370 and OC-capable B350 chipsets. This would also put those who own $300 motherboards such as the X370 XPower out of luck. To recap, AMD announced on numerous occasions that it doesn't want to be a greedy clique like its competitor, by forcing motherboard upgrades and promised that socket AM4 motherboards will be backwards and forwards compatible with at least four generations of Ryzen processors, running all the way up to 2020.

This normally should mean that any 300-series motherboard must support 4th generation Ryzen processors with a simple BIOS update. Most 300-series motherboards, including from MSI, even ship with USB BIOS Flashback feature to help with forwards compatibility. Unfortunately, motherboard companies such as MSI care more about their bottom-lines than the consumer. In a support e-mail to an X370 XPower Titanium owner, MSI confirmed that it will not extend Zen 2 support to AMD 300-series. Other motherboard vendors could follow MSI's suit as a representative of another motherboard vendor, on condition of anonymity, told TechPowerUp that "Zen 2" processors have steeper electrical requirements that 300-series motherboards don't meet. This is an excuse similar to the one Intel gave for the planned obsolescence of its 100-series and 200-series chipsets, even as it was repeatedly proven that those motherboards can run and overclock 9th generation processors with custom firmware just fine. Would MSI care to explain whether a B450M PRO-M2 has a stronger VRM than an X370 XPower Titanium to warrant "Zen 2" support? Will all "Zen 2" processor SKUs have steep electrical requirements? Will there not be any SKUs with double-digit-Watt TDP ratings?

Update (16/04): MSI posted a clarification on this issue.

AMD "Castle Peak," "Rome," and "Matisse" Referenced in Latest AIDA64 Changelog

FinalWire over the past week posted the latest public beta of AIDA64, which adds support for the three key processor product lines based on AMD's "Zen 2" microarchitecture. The "Matisse" multi-chip module, which received extensive coverage over the past few weeks, will be AMD's main derivative of "Zen 2," designed for the client-segment socket AM4 platform, with up to 16 CPU cores, and the initial flagship product featuring 12 cores. "Rome" is AMD's all-important enterprise-segment MCM for the SP3 platform, with up to 64 CPU cores spread across eight 8-core chiplets interfacing a centralized I/O controller die with a monolithic 8-channel memory controller. It so happens that AMD also wants to update its Ryzen Threadripper line of high-end desktop processors, with "Castle Peak."

"Castle Peak" is codename for 3rd generation Ryzen Threadripper and a client-segment derivative of the "Rome" MCM with a reconfigured I/O controller die that has a monolithic 4-channel DDR4 memory interface, and an unspecified number of CPU cores north of 24. This is for backwards compatibility with the existing AMD X399 motherboards. AMD configures core-count by physically changing the number of 8-core chiplets on the MCM, in addition to disabling cores in groups of 2 within the chiplet. The company could scale core counts looking at its competitive environment. The monolithic quad-channel memory interface could significantly improve the chip's memory performance compared to current-generation Threadrippers, particularly the Threadripper WX series chips in which half the CPU cores are memory bandwidth-starved. The AIDA64 update also improves detection of existing Ryzen/EPYC processors with the K17.3 and K17.5 integrated northbridges.

DOWNLOAD: FinalWire AIDA64 Extreme 5.99.4983 beta

AMD to Simultaneously Launch 3rd Gen Ryzen and Unveil Radeon "Navi" This June

TAITRA, the governing body behind the annual Computex trade-show held in Taipei each June, announced that AMD CEO Dr. Lisa Su will host a keynote address which promises to be as exciting as her CES keynote. It is revealed that Dr. Su will simultaneously launch or unveil at least four product lines. High up the agenda is AMD's highly anticipated 3rd generation Ryzen desktop processors in the socket AM4 package, based on "Zen 2" microarchitecture, and a multi-chip module (MCM) codenamed "Matisse." This launch could be followed up by a major announcement related to the company's 2nd generation EPYC enterprise processors based on the "Rome" MCM.

PC enthusiasts are in for a second major announcement, this time from RTG, with a technical reveal or unveiling of Radeon "Navi," the company's first GPU designed from the ground up for the 7 nm silicon fabrication process. It remains to be seen which market-segment AMD targets with the first "Navi" products, and the question on everyone's minds, whether AMD added DXR acceleration, could be answered. Lastly, the company could announce more variants of its Radeon Instinct DNN accelerators.

AMD President and CEO Dr. Lisa Su to Deliver COMPUTEX 2019 CEO Keynote

Taiwan External Trade Development Council (TAITRA) announced today that the 2019 COMPUTEX International Press Conference will be held with a Keynote by AMD President and CEO Dr. Lisa Su. The 2019 COMPUTEX International Press Conference & CEO Keynote is scheduled for Monday, May 27 at 10:00 AM in Room 201 of the Taipei International Convention Center (TICC) in Taipei, Taiwan with the keynote topic "The Next Generation of High-Performance Computing".

"COMPUTEX, as one of the global leading technology tradeshows, has continued to advance with the times for more than 30 years. This year, for the first time, a keynote speech will be held at the pre-show international press conference," said Mr. Walter Yeh, President & CEO, TAITRA, "Dr. Lisa Su received a special invitation to share insights about the next generation of high-performance computing. We look forward to her participation attracting more companies to participate in COMPUTEX, bringing the latest industry insights, and jointly sharing the infinite possibilities of the technology ecosystem on this global stage."

AMD Ryzen 3000 "Zen 2" BIOS Analysis Reveals New Options for Overclocking & Tweaking

AMD will launch its 3rd generation Ryzen 3000 Socket AM4 desktop processors in 2019, with a product unveiling expected mid-year, likely on the sidelines of Computex 2019. AMD is keeping its promise of making these chips backwards compatible with existing Socket AM4 motherboards. To that effect, motherboard vendors such as ASUS and MSI began rolling out BIOS updates with AGESA-Combo 0.0.7.x microcode, which adds initial support for the platform to run and validate engineering samples of the upcoming "Zen 2" chips.

At CES 2019, AMD unveiled more technical details and a prototype of a 3rd generation Ryzen socket AM4 processor. The company confirmed that it will implement a multi-chip module (MCM) design even for their mainstream-desktop processor, in which it will use one or two 7 nm "Zen 2" CPU core chiplets, which talk to a 14 nm I/O controller die over Infinity Fabric. The two biggest components of the IO die are the PCI-Express root complex, and the all-important dual-channel DDR4 memory controller. We bring you never before reported details of this memory controller.

MSI Rolls Out AMD 400-series BIOS Updates with "Zen 2" Microcode

MSI mid-March began quietly rolling out BIOS updates for its socket AM4 motherboards based on AMD 400-series chipset, with a very ominous BIOS change-log entry: "Support new upcoming AMD CPU." At first, we dismissed this for being the company's follow-up to its 6th March announcement of support for some of the newer Athlon processor models, namely the 220GE and 240GE. After updating our MSI B450 Gaming Pro Carbon AC with one of these BIOSes, however, we discovered a very interesting microcode string - AGESA COMBO-AM4 0.0.7.2.

Such a major change in AGESA shouldn't be warranted to add support for two new chips based on existing "Raven Ridge" architecture that both AGESA "Summit Ridge" and AGESA PiR (Pinnacle Ridge) series microcodes should be able to comfortably run. We spoke with sources familiar with AMD microcode, who revealed that this AGESA COMBO-AM4 0.0.7.2 is designed for the upcoming "Zen 2" microarchitecture, and its first socket AM4 implementation, codenamed "Matisse." AMD internal versions of AGESA with Matisse support begin with the version sequence 0.0.7.x., and as we head closer to formal launch of these chips, AMD could release a 1.0.0.0 version of "AGESA COMBO-AM4." For our B450 Gaming Pro Carbon AC, the BIOS version packing this new AGESA is v1.60, and we wager this board should now be able to run Ryzen "Matisse" engineering samples. Now, if we can only get our hands on one.

Intel to Refresh its LGA2066 HEDT Platform This Summer?

Intel is rumored to refresh its high-end desktop (HEDT) platforms this Summer with new products based on the "Cascade Lake" microarchitecture. Intel now has two HEDT platforms, LGA2066 and LGA3647. The new "Cascade Lake-X" silicon will target the LGA2066 platform, and could see the light of the day by June, on the sidelines of Computex 2019. A higher core-count model with 6-channel memory, will be launched for the LGA3647 socket as early as April. So if you've very recently fronted $3,000 on a Xeon W-3175X, here's a bucket of remorse. Both chips will be built on existing 14 nm process, and will bring innovations such as Optane Persistent Memory support, Intel Deep Learning Boost (DLBOOST) extensions with VNNI instruction-set, and hardware mitigation against more variants of "Meltdown" and "Spectre."

Elsewhere in the industry, and sticking with Intel, we've known since November 2018 of the existence of "Comet Lake," which is a 10-core silicon for the LGA1151 platform, and which is yet another "Skylake" derivative built on existing 14 nm process. This chip is real, and will be Intel's last line of defense against AMD's first 7 nm "Zen 2" socket AM4 processors, with core-counts of 12-16.

AMD May Offer Some Insights on Upcoming Ryzen 3000 Series at GDC 2019

AMD's Ryzen 3000 series is one of the most hotly anticipated hardware launches in recent times. I'd say that the hype surrounding AMD's processor launches, unlike Intel's, has become vested with an actual enthusiasm that is likely in our nature - to see the underdog come out with innovative products that reverse market expectations. AMD's processor launches have seen hype levels rivaling - and even surpassing, all of this anecdotally, of course - some GPU launches. It makes sense for AMD to embrace every opportunity it gets to build hype around its products - and it seems the company will be doing just so at GDC 2019, which will run from March 18th through March 22nd.

AMD will be hosting a time slot at GDC 2019 in San Francisco. Hosted by Ken Mitchell, the presentation that has been slotted in to GDC's panels is titled ""AMD Ryzen Processor Software Optimization (Presented by AMD)". As the announcement reads, this presentation is meant to "Learn about the Ryzen line up of processors, profiling tools and techniques to understand optimization opportunities, and get a glimpse of the next generation of "Zen 2" x86 core architecture. Gain insight into code optimization opportunities and lessons learned with examples including C/C++, assembly, and hardware performance-monitoring counters." So no, there won't be any architecture deep dives. But there will be some new information - and we all know that speculating and running through the breadcrumb trail is a huge part of the fun.

No AMD Radeon "Navi" Before October: Report

AMD "Navi" is the company's next-generation graphics architecture succeeding "Vega" and will leverage the 7 nm silicon fabrication process. It was originally slated to launch mid-2019, with probable unveiling on the sidelines of Computex (early-June). Cowcotland reports that AMD has delayed its plans to launch "Navi" all the way to October (Q4-2019). The delay probably has something to do with AMD's 7 nm foundry allocation for the year.

AMD is now fully reliant on TSMC to execute its 7 nm product roadmap, which includes its entire 2nd generation EPYC and 3rd generation Ryzen processors based on the "Zen 2" architecture, and to a smaller extent, GPUs based on its 2nd generation "Vega" architecture, such as the recently launched Radeon VII. We expect the first "Navi" discrete GPU to be a lean, fast-moving product that succeeds "Polaris 30." In addition to 7 nm, it could incorporate faster SIMD units, higher clock-speeds, and a relatively cost-effective memory solution, such as GDDR6.

AMD Updates Wafer Supply Agreement with GlobalFoundries to Free Itself of "7nm Tax"

AMD in its Q4-2018 Earnings Report disclosed that it has amended its Wafer Supply Agreement (WSA) with GlobalFoundries that frees it from paying a "7 nanometer tax." Under the older version of WSA, AMD would have had to pay a penalty to GlobalFoundries if it sourced processors from any other semiconductor foundry. The company got preferential pricing in return for the exclusivity. With GlobalFoundries discontinuing development of cutting-edge processes such as 7 nm and 5 nm, it makes sense for AMD to seek out other foundry partners, such as TSMC, and an amendment to the WSA was needed. With this amendment in place, AMD can go ahead and source 7 nm dies from TSMC without paying penalties to GlobalFoundries (GloFo).

With its "Zen 2" microarchitecture, AMD is going big on multi-chip modules, in which only those components that can tangibly benefit from the switch to the 7 nm node, namely the CPU cores, would be built on 7 nm dies, called "CPU chiplets," while components that don't need the miniaturization just yet, such as the processor's memory controller, PCIe root-complex, etc., will be built on separate dies called "I/O controllers." These dies will continue to be 14 nm, and likely supplied by GloFo. Final packaging of 7 nm CPU chiplets from TSMC, and 14 nm I/O controllers from GloFo, will happen at GloFo's facilities in China or Malaysia. AMD in its amendment committed to purchasing 14 nm and 12 nm chips from GloFo between 2019 and 2021, which means the MCM approach to processors is here to stay.

ASRock Readies Nine AMD X570 Motherboards with "Zen 2" Matisse Support

Sometime mid-2019, AMD will launch its 3rd generation Ryzen "Zen 2" processors with core counts of up to 16 cores in the AM4 package. These processors will launch alongside the new AMD 500-series desktop chipset family, led by the X570. AMD assures backwards compatibility of these processors with older chipsets provided motherboard vendors support their customers with BIOS updates. You'll probably need a 500-series chipset motherboard to use PCI-Express gen 4.0 connectivity, while older chipsets will limit connectivity to gen 3.0 (not that there are any GPUs that use gen 4.0).

ASRock is developing as many as nine motherboard models based on the AMD X570, according to a list scored by VideoCardz. These include the X570 Phantom Gaming X and X570 Taichi leading the top-end; X570 Phantom Gaming 6, X570 Phantom Gaming 4, and X570 Extreme4 covering the mid-range, and the entry-level of the lineup consisting of the X570 Pro4/R2.0 and X570M Pro4/R2.0.

AMD 3rd Gen Ryzen AM4 Package Capable of Two 8-core Chiplets

At its CES 2019 keynote, AMD unveiled two killer client-segment products, the Radeon VII graphics card, which beats the GeForce RTX 2080; and a sneak preview of the 3rd generation Ryzen socket AM4 processor based on the company's "Zen 2" microarchitecture. As part of the unveil, CEO Lisa Su demonstrated an 8-core/16-thread 3rd generation Ryzen prototype processor in a head-to-head CineBench nT face-off with the Intel Core i9-9900K processor, which has the same core-count. The Ryzen narrowly beat the Intel flagship. Following this, Dr. Su held up a de-lidded sibling of the processor that was tested, revealing not one, but two dies.

This confirms that AMD is taking the heterogeneous multi-chip module approach to building its 3rd generation Ryzen processors, much like its 2nd generation EPYC processors that were unveiled late last year. The MCM of the processor Dr. Su held up had two chips, the smaller chip is an 8-core CPU chiplet built on the 7 nm process, that appears to have the same die-size as the 8-core chiplets that make up the 64-core 2nd gen EPYC MCMs, the larger die is an I/O controller logic built on the 14 nm process. This die controls the memory, PCIe, and SoC connectivity of the package. We noticed something curious about the way the two dies are arranged on the package substrate.

AMD's CES 2019 Keynote - Stream & Live Blog

CPUs or GPUs? Ryzen 3000 series up to 16 cores or keeping their eight? Support for raytracing? Navi or die-shrunk Vega for consumer graphics? The questions around AMD's plans for 2019 are still very much in the open, but AMD's Lisa Su's impending livestream should field the answers to many of these questions, so be sure to watch the full livestream, happening in just a moment.

You can find the live stream here, at YouTube.

18:33 UTC: Looking forward, Lisa mentioned a few technology names without giving additional details: "... when you're talking about future cores, Zen 2, Zen 3, Zen 4, Zen 5, Navi, we're putting all of these architectures together, in new ways".

18:20 UTC: New Ryzen 3rd generation processors have been teased. The upcoming processors are based on Zen 2, using 7 nanometer technology. AMD showed a live demo of Forza Horizon 4, using Ryzen third generation, paired with Radeon Vega VII, which is running "consistently over 100 FPS at highest details at 1080p resolution". A second demo, using Cinebench, pitted an 8-core/16-thread Ryzen 3rd generation processor against the Intel Core i9-9900K. The Ryzen CPU was "not final frequency, an early sample". Ryzen achieved a score of 2057 using 135 W, while Intel achieved a score of 2040 using 180 W.. things are looking good for Ryzen 3rd generation indeed. Lisa also confirmed that next-gen Ryzen will support PCI-Express 4.0, which doubles the bandwidth per lane over PCI-Express 3.0. Ryzen third generation will run on the same AM4 infrastructure as current Ryzen; all existing users of Ryzen can simply upgrade to the new processors, when they launch in the middle of 2019 (we think Computex).
Ryzen third generation uses a chiplet design. The smaller die on the right contains 8-cores/16-threads using 7 nanometer technology. The larger die on the left is the IO die, which consists of things like the memory controller and PCI-Express connectivity, to shuffle data between the CPU core die and the rest of the system.

AMD-hired Agency in South Korea Teases AMD Ryzen 7 3700X, Ryzen 5 3600X

Anyone looking for an update to their CPU that didn't quite jump on the Coffee Lake/Zen/Zen+ bandwagon is likely paying close attention to AMD's upcoming Zen 2 CPUs. The upcoming AMD processors will finally leave the company ahead of Intel in terms of manufacturing process for the first time in years, and will bring about AMD's new vision for HCC desktop processors in a chiplet design. With the release of Zen 2 set for 2019 (probably around Computex), and its launch being of such importance to AMD, it isn't that surprising that some promotions/teases are already popping up.

The tease in question was posted by an AMD-contracted Sales agency in South Korea, which launched a campaign inviting users to guess Cinebench scores for upcoming AMD processors: namely, the Ryzen 7 3700X and Ryzen 5 3600X - thus confirming the nomenclature for AMD's upcoming CPUs. The contest finishes on December 14th, and is basically asking users to take a gander on scores for unreleased CPUs - promising prizes of said CPUs when they launch.

AMD 3rd Generation Ryzen Probable SKUs, Specs, Pricing Leaked?

One of our readers tipped us off with a very plausible looking image that drops a motherlode of information about what AMD's 2nd generation Ryzen (aka Ryzen 3000 series) processor lineup could look like. This includes a vast selection of SKUs, their CPU and iGPU core configurations, clock-speeds, and OEM channel pricing. The list speaks of a reentry for 7th generation A-series "Excavator" as Duron X4 series, followed by Duron 300GE-series based on a highly cut down "Raven Ridge," Athlon 300GE 2-core/4-thread based on an implausible "Zen+ 12 nm" APU die, followed by quad-core Ryzen 3 3000 series processors with and without iGPUs, making up the company's entry-level product lineup.

The core counts seem to jump from 4-core straight to 8-core, with no 6-core in between, for the Ryzen 5 series. This is also where AMD's new IP, the 7 nm "Zen 2" architecture, begins. There appears to be a large APU die (or a 3-chip MCM) with an 8-core CPU and 20-CU iGPU, which makes up certain Ryzen 5 SKUs. These chips are either 8-core/8-thread or 8-core/16-thread. The Ryzen 7 series is made up of 12-core/24-thread processors that are devoid of iGPU. The new Ryzen 9 series extension caps off the lineup with 16-core/32-thread SKUs. And these are just socket AM4.

AMD 3rd Generation Ryzen Confirmed for Computex 2019

In a development that could explain why Intel is frantically stitching together 10 cores with the "Comet Lake" silicon, a slide leaked from a private event hosted by motherboard major GIGABYTE reveals that AMD's third generation Ryzen desktop platform could launch as early as Computex 2019 (June). The platform will include AMD's first client-segment processor based on its "Zen 2" microarchitecture, codenamed "Matisse," and its companion chipset, the AMD X570.

3rd generation Ryzen with X570 is expected to be the world's first mainstream desktop platform to feature PCI-Express gen 4.0. AMD could maintain the processor's backwards compatibility with older 300-series and 400-series chipset motherboards by shaping its PCI-Express implementation to use external re-drivers based on the motherboard. This could make 500-series motherboards slightly pricier than current AM4 motherboards. Backwards compatibility could mean that unless you really need PCIe gen 4.0, you should be able to save money by opting for older motherboards.

AMD Doubles L3 Cache Per CCX with Zen 2 "Rome"

A SiSoft SANDRA results database entry for a 2P AMD "Rome" EPYC machine sheds light on the lower cache hierarchy. Each 64-core EPYC "Rome" processor is made up of eight 7 nm 8-core "Zen 2" CPU chiplets, which converge at a 14 nm I/O controller die, which handles memory and PCIe connectivity of the processor. The result mentions cache hierarchy, with 512 KB dedicated L2 cache per core, and "16 x 16 MB L3." Like CPU-Z, SANDRA has the ability to see L3 cache by arrangement. For the Ryzen 7 2700X, it reads the L3 cache as "2 x 8 MB L3," corresponding to the per-CCX L3 cache amount of 8 MB.

For each 64-core "Rome" processor, there are a total of 8 chiplets. With SANDRA detecting "16 x 16 MB L3" for 64-core "Rome," it becomes highly likely that each of the 8-core chiplets features two 16 MB L3 cache slices, and that its 8 cores are split into two quad-core CCX units with 16 MB L3 cache, each. This doubling in L3 cache per CCX could help the processors cushion data transfers between the chiplet and the I/O die better. This becomes particularly important since the I/O die controls memory with its monolithic 8-channel DDR4 memory controller.

AMD Ryzen 7 3700U Shows Up With Lots of Maybes, Could Feature Zen 2

AMD's low-power Ryzen 3700U APU has been leaked. Codenamed ZM370SC4T4MFG_38/22_Y, this latest AMD processor features 4 cores and 8 threads with a base clock of 2.2 GHz and a boost clock of 3.8 GHz, making it very similar to the current generation 2700U. The GPU, which is recognized as Picasso by UserBenchmark, is like just another codename for now, as other applications are listing it as a Radeon RX Vega 10 GPU. Considering the 3000U Series is supposed to be similar to the 2000U offerings it could very well feature the same Vega 10 GPU and still be based on the Zen+ or the Zen 2 architectures. That said, nothing is confirmed, but some slides leaked from Informatica Cero suggest that the Ryzen 7 3700U could indeed feature the Zen 2 architecture. That would be fairly interesting given that the Ryzen family for laptops/convertibles have been a step behind the desktop solutions for a quite some time.

Picasso which we've been hearing about since the codename first appeared in September of 2017, looks to be nothing more than Raven Ridge manufactured on the 12nm node. This is of course based on the information that is available. Some people suggest this new APU could be on the 7 nm node, but this is difficult to believe as AMD is likely to devote 7 nm manufacturing to their EPYC server solutions and Ryzen desktop products first. Therefore Zen 2 APUs for notebooks are likely still far off.

Stuttgart-based HLRS to Build a Supercomputer with 10,000 64-core Zen 2 Processors

Höchstleistungsrechenzentrum (HLRS, or High-Performance Computing Center), based in Stuttgart Germany, is building a new cluster supercomputer powered by 10,000 AMD Zen 2 "Rome" 64-core processors, making up 640,000 cores. Called "Hawk," the supercomputer will be HLRS' flagship product, and will open its doors to business in 2019. The slide-deck for Hawk makes a fascinating disclosure about the processors it's based on.

Apparently, each of the 64-core "Rome" EPYC processors has a guaranteed clock-speed of 2.35 GHz. This would mean at maximum load (with all cores loaded 100%), the processor can manage to run at 2.35 GHz. This is important, because the supercomputer's advertised throughput is calculated on this basis, and clients draw up SLAs on throughput. The advertised peak throughput for the whole system is 24.06 petaFLOP/s, although the company is yet to put out nominal/guaranteed performance numbers (which it will only after first-hand testing). The system features 665 TB of RAM, and 26,000 TB of storage.

AMD "Zen 2" IPC 29 Percent Higher than "Zen"

AMD reportedly put out its IPC (instructions per clock) performance guidance for its upcoming "Zen 2" micro-architecture in a version of its Next Horizon investor meeting, and the numbers are staggering. The next-generation CPU architecture provides a massive 29 percent IPC uplift over the original "Zen" architecture. While not developed for the enterprise segment, the stopgap "Zen+" architecture brought about 3-5 percent IPC uplifts over "Zen" on the backs of faster on-die caches and improved Precision Boost algorithms. "Zen 2" is being developed for the 7 nm silicon fabrication process, and on the "Rome" MCM, is part of the 8-core chiplets that aren't subdivided into CCX (8 cores per CCX).

According to Expreview, AMD conducted DKERN + RSA test for integer and floating point units, to arrive at a performance index of 4.53, compared to 3.5 of first-generation Zen, which is a 29.4 percent IPC uplift (loosely interchangeable with single-core performance). "Zen 2" goes a step beyond "Zen+," with its designers turning their attention to critical components that contribute significantly toward IPC - the core's front-end, and the number-crunching machinery, FPU. The front-end of "Zen" and "Zen+" cores are believed to be refinements of previous-generation architectures such as "Excavator." Zen 2 gets a brand-new front-end that's better optimized to distribute and collect workloads between the various on-die components of the core. The number-crunching machinery gets bolstered by 256-bit FPUs, and generally wider execution pipelines and windows. These come together yielding the IPC uplift. "Zen 2" will get its first commercial outing with AMD's 2nd generation EPYC "Rome" 64-core enterprise processors.

Update Nov 14: AMD has issued the following statement regarding these claims.
As we demonstrated at our Next Horizon event last week, our next-generation AMD EPYC server processor based on the new 'Zen 2' core delivers significant performance improvements as a result of both architectural advances and 7nm process technology. Some news media interpreted a 'Zen 2' comment in the press release footnotes to be a specific IPC uplift claim. The data in the footnote represented the performance improvement in a microbenchmark for a specific financial services workload which benefits from both integer and floating point performance improvements and is not intended to quantify the IPC increase a user should expect to see across a wide range of applications. We will provide additional details on 'Zen 2' IPC improvements, and more importantly how the combination of our next-generation architecture and advanced 7nm process technology deliver more performance per socket, when the products launch.

AMD Zen 2 "Rome" MCM Pictured Up Close

Here is the clearest picture of AMD "Rome," codename for the company's next-generation EPYC socket SP3r2 processor, which is a multi-chip module of 9 chiplets (up from four). While first-generation EPYC MCMs (and Ryzen Threadripper) were essentially "4P-on-a-stick," the new "Rome" MCM takes the concept further, by introducing a new centralized uncore component called the I/O die. Up to eight 7 nm "Zen 2" CPU dies surround this large 14 nm die, and connect to it via substrate, using InfinityFabric, without needing a silicon interposer. Each CPU chiplet features 8 cores, and hence we have 64 cores in total.

The CPU dies themselves are significantly smaller than current-generation "Zeppelin" dies, although looking at their size, we're not sure if they're packing disabled integrated memory controllers or PCIe roots anymore. While the transition to 7 nm can be expected to significantly reduce die size, groups of two dies appear to be making up the die-area of a single "Zeppelin." It's possible that the CPU chiplets in "Rome" physically lack an integrated northbridge and southbridge, and only feature a broad InfinityFabric interface. The I/O die handles memory, PCIe, and southbridge functions, featuring an 8-channel DDR4 memory interface that's as monolithic as Intel's implementations, a PCI-Express gen 4.0 root-complex, and other I/O.

AMD Unveils "Zen 2" CPU Architecture and 7 nm Vega Radeon Instinct MI60 at New Horizon

AMD today held its "New Horizon" event for investors, offering guidance and "color" on what the company's near-future could look like. At the event, the company formally launched its Radeon Instinct MI60 GPU-based compute accelerator; and disclosed a few interesting tidbits on its next-generation "Zen 2" mircroarchitecture. The Instinct MI60 is the world's first GPU built on the 7 nanometer silicon fabrication process, and among the first commercially available products built on 7 nm. "Rome" is on track to becoming the first 7 nm processor, and is based on the Zen 2 architecture.

The Radeon Instinct MI60 is based on a 7 nm rendition of the "Vega" architecture. It is not an optical shrink of "Vega 10," and could have more number-crunching machinery, and an HBM2 memory interface that's twice as wide that can hold double the memory. It also features on-die logic that gives it hardware virtualization, which could be a boon for cloud-computing providers.

AMD's Zen 2 Could be Revealed on November 6th, "Next Horizon" Event Scheduled

AMD Investor Relations will host a "Next Horizon" event on November 6th, and although there is no confirmation on what products will be announced there, the title alone makes us think about AMD's Zen 2 architecture. The company has just explained that on that day their executives will "discuss the innovation of AMD products and technology, specifically designed with the datacenter on industry-leading 7 nm process technology". AMD announced Ryzen and quite a lot of details about the Zen's processors on their last "Horizon" event, so it seems plausible that the incoming event will be perfect to talk about its next-gen architecture. That focus on the 7 nm process technology will probably make AMD talk about their new Vega graphics, but it seems end users will have to wait, as datacenters come first.

AMD Could Solve Memory Bottlenecks of its MCM CPUs by Disintegrating the Northbridge

AMD sprung back to competitiveness in the datacenter market with its EPYC enterprise processors, which are multi-chip modules of up to four 8-core dies. Each die has its own integrated northbridge, which controls 2-channel DDR4 memory, and a 32-lane PCI-Express gen 3.0 root complex. In applications that can not only utilize more cores, but also that are memory bandwidth intensive, this approach to non-localized memory presents design bottlenecks. The Ryzen Threadripper WX family highlights many of these bottlenecks, where video encoding benchmarks that are memory-intensive see performance drops as dies without direct access to I/O are starved of memory bandwidth. AMD's solution to this problem is by designing CPU dies with a disabled northbridge (the part of the die with memory controllers and PCIe root complex). This solution could be implemented in its upcoming 2nd generation EPYC processors, codenamed "Rome."

With its "Zen 2" generation, AMD could develop CPU dies in which the integrated northrbidge can be completely disabled (just like the "compute dies" on Threadripper WX processors, which don't have direct memory/PCIe access relying entirely on InfinityFabric). These dies talk to an external die called "System Controller" over a broader InfinityFabric interface. AMD's next-generation MCMs could see a centralized System Controller die that's surrounded by CPU dies, which could all be sitting on a silicon interposer, the same kind found on "Vega 10" and "Fiji" GPUs. An interposer is a silicon die that facilitates high-density microscopic wiring between dies in an MCM. These explosive speculative details and more were put out by Singapore-based @chiakokhua, aka The Retired Engineer, a retired VLSI engineer, who drew block diagrams himself.
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