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Arm Delivers New Edge Processor IPs for IoT

Today, Arm announced significant additions to its artificial intelligence (AI) platform, including new machine learning (ML) IP, the Arm Cortex -M55 processor and Arm Ethos -U55 NPU, the industry's first microNPU (Neural Processing Unit) for Cortex-M, designed to deliver a combined 480x leap in ML performance to microcontrollers. The new IP and supporting unified toolchain enable AI hardware and software developers with more ways to innovate as a result of unprecedented levels of on-device ML processing for billions of small, power-constrained IoT and embedded devices.

NVIDIA's Next-Generation "Ampere" GPUs Could Have 18 TeraFLOPs of Compute Performance

NVIDIA will soon launch its next-generation lineup of graphics cards based on a new and improved "Ampere" architecture. With the first Tesla server cards that are a part of the Ampere lineup going inside Indiana University Big Red 200 supercomputer, we now have some potential specifications and information about its compute performance. Thanks to the Twitter user dylan552p(@dylan522p), who did some math about the potential compute performance of the Ampere GPUs based on NextPlatform's report, we discovered that Ampere is potentially going to feature up to 18 TeraFLOPs of FP64 compute performance.

With Big Red 200 supercomputer being based on Cray's Shasta supercomputer building block, it is being deployed in two phases. The first phase is the deployment of 672 dual-socket nodes powered by AMD's EPYC 7742 "Rome" processors. These CPUs provide 3.15 PetaFLOPs of combined FP64 performance. With a total of 8 PetaFLOPs planned to be achieved by the Big Red 200, that leaves just a bit under 5 PetaFLOPs to be had using GPU+CPU enabled system. Considering the configuration of a node that contains one next-generation AMD "Milan" 64 core CPU, and four of NVIDIA's "Ampere" GPUs alongside it. If we take for a fact that Milan boosts FP64 performance by 25% compared to Rome, then the math shows that the 256 GPUs that will be delivered in the second phase of Big Red 200 deployment will feature up to 18 TeraFLOPs of FP64 compute performance. Even if "Milan" doubles the FP64 compute power of "Rome", there will be around 17.6 TeraFLOPs of FP64 performance for the GPU.

Intel to Detail Xe Graphics Card Architecture at GDC

This year's Game Developers Conference (GDC) that will take place in March is forming to become a very interesting one. According to the GDC schedule platform, Intel is having a presentation about its upcoming Xe graphics card architecture. Saying that "Intel's brand new Xe Architecture, has been teased for a while, and is scheduled for release later this year! This update brings a significant compute, geometry and throughput improvements over today's widely used Gen9 and Gen11 graphics.", Intel is giving us a slight hint of what is to come.

Presented by Intel's senior developer relations engineer, Antonie Cohade, the talk will include an in-depth look of the Xe hardware architecture and its implementations. Said to introduce "powerful new features", the talk about Xe graphics should include a mention of the latest trend in the world of 3D graphics, ray tracing, and show us what are the capabilities of the new GPU architecture.

Intel Unveils Xe DG1-SDV Graphics Card, Demonstrates Intent to Seriously Compete in the Gaming Space

At a media event on Wednesday, Intel invited us to check out their first working modern discrete graphics card, the Xe DG1 Software Development Vehicle (developer-edition). Leading the event was our host Ari Rauch, Intel Vice President and General Manager for Graphics Technology Engineering and dGPU Business. Much like gruff developer-editions of game consoles released to developers several quarters ahead of market launch, the DG1-SDV allows software developers to discover and learn the Xe graphics architecture, and develop optimization processes for their current and future software within their organizations. We walked into the event expecting to see a big ugly PCB with a bare fan-heatsink and a contraption that sort-of looks like a graphics card; but were pleasantly surprised with what we saw: a rather professional product design.

What we didn't get at the event, through, was a juicy technical breakdown of the Xe graphics architecture, and its various components that add up to the GPU. We still left pleasantly surprised for what we were shown: it works! The DG1-SDV is able to play games at 1080p, even if they are technically lightweight titles like "Warframe," and aren't maxing out settings. The SDV is a 15.2 cm-long graphics card that relies on the PCI-Express slot for power entirely (and hence pulling less than 75 W).

Intel CPU Based on New Architecture Leaks

Today Intel's CPU based on yet unannounced architecture got revealed in the SiSoft benchmark database. Featuring six cores and twelve threads running at 3 GHz, it appears like a regular 14 nm CPU that's already available, however, when digging through the details, many things are revealed. The newly submitted CPU has a different L2 cache configuration from previous CPU offerings, with this chip featuring 1.25 MB of L2 cache per core, it is unlike anything else Intel currently offers. Ice Lake mobile chips feature 512 KB, while the highest amount of L2 cache is currently present on i9-10980XE, which features 1 MB of L2.

It is unknown where this CPU fits in the whole 14/10 nm lineup, as we don't know if this is an iteration of 10 nm Tiger Lake or the rumored 14 nm Rocket Lake CPU. All we know is that this CPU features new architecture compared to Skylake iterations that are currently being used, judging by L2 cache bump, which usually happens on new architectures. The platform used for benchmarking this CPU was SuperMicro X12DAi-N SMC X12 dual-socket motherboard, which featured two of these new CPUs for a total of 12 cores and 24 threads.

Ray Tracing and Variable-Rate Shading Design Goals for AMD RDNA2

Hardware-accelerated ray tracing and variable-rate shading will be the design focal points for AMD's next-generation RDNA2 graphics architecture. Microsoft's reveal of its Xbox Series X console attributed both features to AMD's "next generation RDNA" architecture (which logically happens to be RDNA2). The Xbox Series X uses a semi-custom SoC that features CPU cores based on the "Zen 2" microarchitecture and a GPU based on RDNA2. It's highly likely that the SoC could be fabricated on TSMC's 7 nm EUV node, as the RDNA2 graphics architecture is optimized for that. This would mean an optical shrink of "Zen 2" to 7 nm EUV. Besides the SoC that powers Xbox Series X, AMD is expected to leverage 7 nm EUV for its RDNA2 discrete GPUs and CPU chiplets based on its "Zen 3" microarchitecture in 2020.

Variable-rate shading (VRS) is an API-level feature that lets GPUs conserve resources by shading certain areas of a scene at a lower rate than the other, without perceptible difference to the viewer. Microsoft developed two tiers of VRS for its DirectX 12 API, tier-1 is currently supported by NVIDIA "Turing" and Intel Gen11 architectures, while tier-2 is supported by "Turing." The current RDNA architecture doesn't support either tiers. Hardware-accelerated ray-tracing is the cornerstone of NVIDIA's "Turing" RTX 20-series graphics cards, and AMD is catching up to it. Microsoft already standardized it on the software-side with the DXR (DirectX Raytracing) API. A combination of VRS and dynamic render-resolution will be crucial for next-gen consoles to achieve playability at 4K, and to even boast of being 8K-capable.

AWS Starts Designing 32-Core Arm Neoverse N1 CPU for Data Center

Amazon Web Services, a part of Amazon that is in charge of all things cloud, has announced plans to release 32 core CPU based on Arm Neoverse N1 microarchitecture that is designed to handle a diverse workload that today's cloud infrastructure needs. This new CPU should be the second iteration of AWS'es custom CPU based on the Arm architecture. First-generation AWS CPU was a processor called Graviton, which Amazon offered on-demand in the cloud.

The still-unnamed second-gen CPU will utilize a 7 nm manufacturing process if the Neoverce N1 core at its base is to be believed. Additionally, everything from the Neoverse line should translate to this next-gen CPU as well, meaning that there will be features like high frequency and high single-threaded performance, cache coherency, and interconnect fabric designed to connect special-purpose accelerators to the CPU complex. For reference, Arm's design of Neoverce N1 has a TDP of 105 W for the whole SoC and its packs 64 cores running at 3.1 GHz, delivering amazing power efficiency and high core count.

AMD "Zen 3" Microarchitecture Could Post Significant Performance Gains

At its recent SC19 talk, AMD touched upon its upcoming "Zen 3" CPU microarchitecture. Designed for the 7 nm EUV silicon fabrication process that significantly increases transistor densities, "Zen 3" could post performance gains "right in line with what you would expect from an entirely new architecture," states AMD, referring to the roughly 15 percent IPC gains that were expected of "Zen 2" prior to its launch. "Zen 2" IPC ended up slightly over 15 percent higher than that of the original "Zen" microarchitecture. AMD's SC19 comments need not be a guidance on the IPC itself, but rather performance gains of end-products versus their predecessors.

The 7 nm EUV process, with its 20 percent transistor-density increase could give AMD designers significant headroom to increase clock speeds to meet the company's generational performance improvement targets. Another direction in which "Zen 3" could go is utilizing the additional transistor density to bolster its core components to support demanding instruction-sets such as AVX-512. The company's microarchitecture is also missing something analogous to Intel's DLBoost, an instruction-set that leverages fixed-function hardware to accelerate AI-DNN building and training. Even VIA announced an x86 microarchitecture with AI hardware and AVX-512 support. In either case, the design of "Zen 3" is complete. We'll have to wait until 2020 to find out how fast "Zen 3" is, and the route taken to get there.

AMD Could Launch Next Generation RDNA 2 GPUs at CES 2020

According to the findings of a Chiphell user called "wjm47196", AMD is supposedly going to host an event at CES 2020 to showcase its next generation of Radeon graphics cards. Having seen huge success with its first-generation "RDNA" GPUs, AMD is expected to showcase improved lineup utilizing new and improved RDNA 2 graphics card architecture.

Judging by the previous information, second generation of RDNA graphics cards will get much-needed features like ray tracing, to remain competitive with existing offers from NVIDIA and soon Intel. Supposed to be built using the 7 nm+ manufacturing process, the new GPU architecture will get around 10-15% performance improvement due to the new manufacturing process alone, with possibly higher numbers if there are changes to the GPU core.

Intel CPUs Since Haswell Vulnerable to "Zombieload v2" Attacks, "Cascade Lake" Included

All Intel CPU microarchitectures since 2013 are vulnerable to a new class of "Zombieload," attacks, chronicled under "Zombieload v2" (CVE-2019-11135). This is the fifth kind of microarchitectural data sampling (MDS) vulnerability, besides the four already disclosed and patched against in Q2-2019. The vulnerability was kept secret by the people who discovered it, as Intel was yet to develop a mitigation against it. There is no silicon-level hardening against it, and Intel has released a firmware-level mitigation that will be distributed by motherboard manufacturers as BIOS updates, or perhaps even OS vendors. While Intel's latest enterprise and HEDT microarchitecture, "Cascade Lake" was thought to be immune to "Zombieload," it's being reported that "Zombieload v2" attacks can still compromise a "Cascade Lake" based server or HEDT that isn't patched.

"Zombieload v2" is an exploitation of the Asynchronous Abort operation of Transactional Synchronization Extensions (TSX), which occurs when malware creates read operation conflicts within the CPU. This reportedly leaks data about what else is being processed. "The main advantage of this approach is that it also works on machines with hardware fixes for Meltdown, which we verified on an i9-9900K and Xeon Gold 5218," reads the latest version of the Zombieload whitepaper that's been updated with "Zombieload v2" information. TSX is a requisite for "Zombieload v2," and all Intel microarchitectures since "Haswell" feature it. AMD processors are inherently immune to "Zombieload v2" as they lack TSX. Intel downplayed the severity or prevalence of "Zombieload v2," but dispatched microcode updates flagged "critical" nevertheless.

AMD Announces Ryzen 9 3950X, Details 3rd Gen Ryzen Threadripper, unlocked Athlon 3000G

AMD today announced four new desktop processors across three very diverse markets. To begin with, the company crowned its socket AM4 mainstream desktop platform with the mighty new Ryzen 9 3950X processor. Next up, it released its new baseline entry-level APU, the Athlon 3000G. Lastly, it detailed the 3rd generation Ryzen Threadripper HEDT processor family with two initial models, the Ryzen Threadripper 3960X and the flagship Ryzen Threadripper 3970X. The company also formally released its AGESA Combo PI 1.0.0.4B microcode, and with it, introduced a killer new feature for all "Zen 2" based Ryzen processors, called ECO Mode.

The Ryzen 9 3950X is a 16-core/32-thread processor in the AM4 package, compatible with all socket AM4 motherboards, provided they have the latest BIOS update with AGESA Combo PI 1.0.0.4B microcode. The processor comes with clock-speeds of 3.50 GHz base, with 4.70 GHz maximum boost frequency, and the same 105 W TDP as the 12-core Ryzen 9 3900X. With 512 KB of dedicated L2 cache per core, and 64 MB of shared L3 cache, the chip has a mammoth 72 MB of "total cache."

Intel CFO Talks About 7nm Rollout, Delay in 10nm, Increased Competition from AMD

Intel CFO George Davis in an interview with Barron's commented on the company's financial health, and some of the reasons behind its rather conservative gross margin guidance looking forward to at least 2023. Intel's current product stack is moving on to the company's 10 nm silicon fabrication process in a phased manner. The company is allocating 10 nm to mobile processors and enterprise processors, while brazening it out with 14 nm on the client-desktop and HEDT platforms until they can build 10 nm desktop parts. AMD has deployed its high-IPC "Zen 2" microarchitecture on TSMC's 7 nm DUV process, with plans to go EUV in the coming months.

"We're still keenly focused on gross margin. Everything from capital efficiency to the way we're designing our products. What we've said though, the delay in 10 nanometer means that we're going to be a little bit disadvantaged on unit cost for a period of time. We actually gave guidance for gross margin out in 2021 to help people understand. 2023 is the period that we were ultimately guiding [when] we're going to see very strong revenue growth and margin expansion. We've got to get through this period where we have the 10 nanometer being a little bit late [as] we're not optimized on a node that we're on. But [by] then we're moving to a two to two and a half year cadence on the next nodes. So we're pulling in the spending on 7 nanometer, which will start up in the second half of 2021 because we think it's the right thing to do competitively," he said.

Intel Scraps 10nm for Desktop, Brazen it Out with 14nm Skylake Till 2022?

In a shocking piece of news, Intel has reportedly scrapped plans to launch its 10 nm "Ice Lake" microarchitecture on the client desktop platform. The company will confine its 10 nm microarchitectures, "Ice Lake" and "Tiger Lake" to only the mobile platform, while the desktop platform will see derivatives of "Skylake" hold Intel's fort under the year 2022! Intel gambles that with HyperThreading enabled across the board and increased clock-speeds, it can restore competitiveness with AMD's 7 nm "Zen 2" Ryzen processors with its "Comet Lake" silicon that offers core-counts of up to 10.

"Comet Lake" will be succeeded in 2021 by the 14 nm "Rocket Lake" silicon, which somehow combines a Gen12 iGPU with "Skylake" derived CPU cores, and possibly increased core-counts and clock speeds over "Comet Lake." It's only 2022 that Intel will ship out a truly new microarchitecture on the desktop platform, with "Meteor Lake." This chip will be built on Intel's swanky 7 nm EUV silicon fabrication node, and possibly integrate CPU cores more advanced than even "Willow Cove," possibly "Golden Cove."

Intel Mobility Xe GPUs to Feature Up to Twice the Performance of Previous iGPUs

Intel at the Intel Developer Conference 'IDC' 2019 in Tokyo revealed their performance projections for mobility Xe GPUs, which will supersede their current consumer-bound UHD620 graphics under the Gen 11 architecture. The company is being vocal in that they can achieve an up to 2x performance uplift over their previous generation - but that will likely only take place in specific scenarios, and not as a rule of thumb. Just looking at Intel's own performance comparison graphics goes to show that we're mostly looking at between 50% and 70% performance improvements in popular eSports titles, which are, really, representative of most of the gaming market nowadays.

The objective is to reach above 60 FPS in the most popular eSports titles, something that Gen 11 GPUs didn't manage with their overall IPC and dedicated die-area. We've known for some time that Intel's Xe (as in, exponential) architecture will feature hardware-based raytracing, and the architecture is being developed for scalability that goes all the way from iGPUs to HPC platforms.

AMD Radeon RX 5500 Gets Benchmarked

AMD is preparing lower-end variants of its NAVI GPUs based on new RDNA graphics card architecture, which will replace all the existing cards based on aging GCN architecture. Today, AMD's upcoming Radeon RX 5500, as it is called, got benchmarked in GFXBench - a cross-platform benchmark which features various kinds of test for Windows, MacOS, iOS and Android.

The benchmark was run on Windows OS using OpenGL API. It only ran the "Manhattan" high-level test, which yielded a result of 5430 frames in total or about 87.6 frames per second. When compared to something like RX 5700 XT, which scored 8905 frames in total and 143.6 FPS, RX 5500 clearly seems positioned at the lower end of NAVI GPU stack. Despite the lack of details, we can expect this card to compete against NVIDIA's GeForce GTX 1660/1660 Ti GPUs where AMD has no competing offer so far.

Researchers Build a CPU Without Silicon Using Carbon Nanotubes

It is no secret that silicon manufacturing is an expensive and difficult process which requires big investment and a lot of effort to get right. Take Intel's 10 nm for example. It was originally planned to launch in 2015, but because of technical difficulties, it got delayed for 2019. That shows how silicon scaling is getting more difficult than ever, while costs are rising exponentially. Development of newer nodes is expected to cost billions of Dollars more, just for the research alone and that is not even including the costs for the setting up a manufacturing facility. In order to prepare for the moment when the development of ever-decreasing size nodes becomes financially and physically unfeasible, researchers are exploring new technologies that could replace and possibly possess even better electrical properties than silicon. One such material (actually a structure made from it) is Carbon Nanotube or CNT in short.

Researchers from MIT, in collaboration with scientists from Analog Devices, have successfully built a CPU based on RISC-V architecture entirely using CNTs. Called RV16X Nano, this CPU is currently only capable of executing a classic "Hello World" program. CNT is a natural semiconductor, however, when manufactured, it is being made as a metallic nanotube. That is due to the fact that metallic nanotubes are easier to integrate into the manufacturing ecosystem. Its has numerous challenges in production because CNTs tend to position themselves randomly in XYZ axes. Researchers from MIT and Analog Devices solved this problem by making large enough surfaces so that enough random tubes are positioned well.

AMD Designing Zen 4 for 2021, Zen 3 Completes Design Phase, out in 2020

AMD in its 2nd generation EPYC processor launch event announced that it has completed the design phase of its next-generation "Zen 3" CPU microarchitecture, and is currently working on its successor, the "Zen 4." AMD debuted its "Zen 2" microarchitecture with the client-segment 3rd generation Ryzen desktop processor family, it made its enterprise debut with the 2nd generation EPYC. This is the first x86 CPU microarchitecture designed for the 7 nanometer silicon fabrication process, and is being built on a 7 nm DUV (deep ultraviolet) node at TSMC. It brings about double-digit percentage IPC improvements over "Zen+."

The "Zen 3" microarchitecture is designed for the next big process technology change within 7 nm, EUV (extreme ultraviolet), which allows significant increases in transistor densities, and could facilitate big improvements in energy-efficiency that could be leveraged to increase clock-speeds and performance. It could also feature new ISA instruction-sets. With "Zen 3" passing design phase, AMD will work on prototyping and testing it. The first "Zen 3" products could debut in 2020. "Zen 4" is being designed for a different era.

Intel Starts Shipping 10 nm Ice Lake CPUs to OEMs

During its second quarter earnings call, Intel announced that it has started shipping of 10th generation "Core" CPUs to OEMs. Making use of 10 nm lithography, the 10th generation of "Core" CPUs, codenamed Ice Lake, were qualified by OEMs earlier in 2019 in order to be integrated into future products. Ice Lake is on track for holiday season 2019, meaning that we can expect products on-shelves by the end of this year. That is exciting news as the 10th generation of Core CPUs is bringing some exciting micro-architectural improvements along with the long awaited and delayed Intel's 10nm manufacturing process node.

The new CPUs are supposed to get around 18% IPC improvement on average when looking at direct comparison to previous generation of Intel CPUs, while being clocked at same frequency. This time, even regular mobile/desktop parts will get AVX512 support, alongside VNNI and Cryptography ISA extensions that are supposed to bring additional security and performance for the ever increasing number of tasks, especially new ones like Neural Network processing. Core configurations will be ranging from dual core i3 to quad core i7, where we will see total of 11 models available.

AMD Radeon RX 5700 XT Confirmed to Feature 64 ROPs: Architecture Brief

AMD "Navi 10" is a very different GPU from the "Vega 10," or indeed the "Polaris 10." The GPU sees the introduction of the new RDNA graphics architecture, which is the first big graphics architecture change on an AMD GPU in nearly a decade. AMD had in 2011 released its Graphics CoreNext (GCN) architecture, and successive generations of GPUs since then, brought generational improvements to GCN, all the way up to "Vega." At the heart of RDNA is its brand new Compute Unit (CU), which AMD redesigned to increase IPC, or single-thread performance.

Before diving deeper, it's important to confirm two key specifications of the "Navi 10" GPU. The ROP count of the silicon is 64, double that of the "Polaris 10" silicon, and same as "Vega 10." The silicon has sixteen render-backends (RBs), these are quad-pumped, which work out to an ROP count of 64. AMD also confirmed that the chip has 160 TMUs. These TMUs are redesigned to feature 64-bit bi-linear filtering. The Radeon RX 5700 XT maxes out the silicon, while the RX 5700 disables four RDNA CUs, working out to 144 TMUs. The ROP count on the RX 5700 is unchanged at 64.

MSI CEO: AMD Plans to Stop Being the Value Alternative, X570 Motherboards to be Expensive

MSI's CEO Charles Chiang, quoted by Tom's Hardware at COMPUTEX 2019, laid out what we were already seeing with motherboard designs from all vendors of AMD's X570-based motherboards: pricing is likely increasing across the board, and AMD's market positioning won't be of the alternative, lower-value brand.

As quoted, Chiang said that ""Lots of people ask me, what do you think about today's AMD? I say today's AMD is completely different company compared to two, three, five years ago. They have nice technology and they are there to put the higher spec with the reasonable pricing. But right now they say, "Hey Charles, let's push to marketing to the higher [end]. So let's sell higher-pricing motherboards, higher-spec motherboards, and let's see what will happen in the market. So I don't think that AMD is the company that wants to sell low cost here, low cost there." Which does make sense: AMD isn't in the position of the underdog anymore -at least technology and product-portfolio wise when it comes to consumer CPUs. With better products, comes a desire for higher margins, and a change in direction for a company that was basically forced to almost cut itself out of the market in terms of profits with its previous, non-competitive CPU designs.

The EPI Announces Successful First Steps Towards a Made-in-Europe High-performance Microprocessor

The European Processor Initiative(EPI), crucial element of the European exascale strategy, delivers its first architectural design to the European Commission and welcomes new partners Almost six months in, the project that kicked off last December has already delivered its first architectural designs to the European Commission, thus marking initial milestones successfully executed. The project that will be the cornerstone of the EU's strategic plans in HPC initially brought together 23 partners from 10 European countries, but has now welcomed three more strong additions to its EPI family. EPI consortium aims to bring a low-power microprocessor to the market and ensure that the key competences for high-end chip design remain in Europe. The European Union's Horizon 2020 program funds this project with a special Framework Partnership Agreement. The initial stage is a three-year Specific Grant Agreement, which lasts until November 2021.

AMD Halts Further x86 Technology Licensing to China

AMD Lisa Su at Computex 2019 confirmed to Tom's hardware that the company wasn't licensing anymore of its x86 IP portfolio to China-based companies. AMD entered a technology license agreement with China's Tianjin Haiguang Advanced Technology Investment Co. Ltd. (THATIC) in 2016. As part of the agreement to license its x86 and SoC IP for chip development, AMD received a cash infusion worth $293 million (plus royalties).

As a result, Chinese chipmaker Hygon started delivering their "Dhyana" CPUs, which looked like copies of AMD's Zen-based Epyc chips with added, Chinese-government approved cryptographic capabilities. AMD had to go through some hoops to get this deal done, but it did. However, now the technology refinement pipe is draining for the Chinese companies, as AMD won't be delivering its post-Zen updates to the core design. It remains to be seen if AMD's intellectual property was enough for Chinese companies to ignite their own in-country CPU development, or if the ongoing US-China trade war will keep on draining the company of CPU independence.

AMD and Samsung Announce Strategic Partnership in Ultra Low Power, High Performance Graphics Technologies with RDNA

AMD and Samsung today announced a key strategic partnership in high performance graphics technologies for the mobile space. The agreement means that Samsung will license AMD's Radeon graphics IP in its latest RDNA iteration, no less, for integration on smartphone graphics processing. Let me stress how impressive this can be: that AMD developed a graphics architecture that can scale from a high-performance GPU down to a nimble, fast, power-sipping module for mobile graphics processing.

This is a huge strategic win for AMD, in that more and more products will be infused with their technology. As Lisa Su puts it, the Radeon user base and development ecosystem will be greatly increased with this Samsung integration - as will AMD's revenue, for sure. Perhaps we'll see a "Powered by AMD Radeon" sticker or engraving in our future Samsung smartphones, as we do with Leica partnerships, for example.)

Rumor: AMD Navi a Stopgap, Hybrid Design of RDNA and GraphicsCoreNext

The Wheel of Rumors turns, and assumptions come and pass, sometimes leaving unfulfilled hopes and dreams. In this case, the rumor mill, in what seems like a push from sweclockers, places Navi not as a "built from the ground-up" architecture, but rather as a highly customized iteration of GCN - iterated in the parts that it actually implements AMD's RDNA architecture, to be exact. And this makes sense from a number of reasons - it's certainly not anything to cry wolf about.

For one, AMD's GCN has been a mainstay in the graphics computing world since it was first introduced back in 2012, succeeding the company's TeraScale architecture. Game engines and assorted software have been well optimized already to take advantage of AMD's design - even with its two ISAs and assorted improvements over the years. One of the most important arguments is derived from this optimization effort: AMD's custom designs for the console market employ architectures that are GCN-based, and thus, any new architecture that would be used by both Microsoft and Sony for their next-generation consoles would have to be strictly backwards compatible.

ARM Revokes Huawei's Chip IP Licence

As the trade war between the US and China continues to unfold, we are seeing major US companies ban or stop providing service to China's technology giant Huawei. Now, it looks like the trade war has crossed the ocean and reached the UK. This time, UK based ARM Holdings, the provider of mobile chip IP for nearly all smartphones and tablets, has revoked the license it has given Huawei.

According to the BBC, ARM Holdings employees were instructed to suspend all interactions with Huawei, and to send a note informing Huawei that "due to an unfortunate situation, they were not allowed to provide support, deliver technology (whether software, code, or other updates), engage in technical discussions, or otherwise discuss technical matters with Huawei, HiSilicon or any of the other named entities." The news came from an internal ARM document the BBC has obtained.
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