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Movespeed SSD N3000 512 GB (88SS1100 + TLC)

512 GB
Capacity
88SS1100
Controller
TLC
Flash
PCIe 3.0 x4
Interface
M.2 2280
Form Factor

Multiple hardware versions found.

Performance could vary due to unannounced flash/controller changes.

SSD Controller
Controller
NAND Die
NAND Die
The Movespeed SSD N3000 is a solid-state drive in the M.2 2280 form factor. It is only available in the 512 GB capacity listed on this page. With the rest of the system, the Movespeed SSD N3000 interfaces using a PCI-Express 3.0 x4 connection. The SSD controller is the 88SS1100 Whistler from Marvell, a DRAM cache chip is available. Movespeed has installed 128-layer TLC NAND flash on the SSD N3000, the flash chips are made by YMTC. Please note that this SSD is sold in multiple variants with different NAND flash or controller, which could affect performance, the "Notes" section at the end of this page has more info. To improve write speeds, a pseudo-SLC cache is used, so bursts of incoming writes are soaked up more quickly. The SSD N3000 is rated for sequential read speeds of up to 3,500 MB/s and 2,200 MB/s write; random IOPS reach up to 300K for reads and 278K for writes.
At its launch, the SSD was priced at 50 USD. The warranty length is set to five years, which is an excellent warranty period. Movespeed guarantees an endurance rating of 320 TBW, a typical value for consumer SSDs.

Solid-State-Drive

Capacity: 512 GB
Overprovisioning: 35.2 GB / 7.4 %
Production: Active
Released: Unknown
Price at Launch: 50 USD
Part Number: YSSDMP-512GN3000
Market: Consumer

Physical

Form Factor: M.2 2280 (Single-Sided)
Interface: PCIe 3.0 x4
Protocol: NVMe 1.3
Power Draw: Unknown

Controller

Manufacturer: Marvell
Name: 88SS1100 Whistler
Architecture: ARM 32-bit Cortex-R5
Core Count: Quad-Core
Foundry: TSCM
Process: 28 nm
Flash Channels: 8 @ 800 MT/s
Chip Enables: 8
Controller Features: DRAM (enabled)

NAND Flash

Manufacturer: YMTC
Name: Xtacking 2.0 (CDT1B)
Type: TLC
Technology: 128-layer
Speed: 1600 MT/s
Capacity: 2 chips @ 2 Tbit
ONFI: 4.1
Topology: Charge Trap
Die Size: 60 mm²
(8.5 Gbit/mm²)
Dies per Chip: 4 dies @ 512 Gbit
Planes per Die: 4
Decks per Die: 2
Word Lines: 141 per NAND String
90.8% Vertical Efficiency
Read Time (tR): 50 µs
Program Time (tProg): 620 µs
Block Erase Time (tBERS): 9.0 ms
Die Read Speed: 1280 MB/s
Die Write Speed: 70 MB/s
Endurance:
(up to)
3000 P/E Cycles
Page Size: 16 KB
Block Size: 2304 Pages
Plane Size: 1980 Blocks

DRAM Cache

Type: DDR3L-1600 CL11
Name: NANYA NT5CC128M16JR-EK
Capacity: 512 MB
(2x 256 MB)
Organization: 2Gx16

Performance

Sequential Read: 3,500 MB/s
Sequential Write: 2,200 MB/s
Random Read: 300,000 IOPS
Random Write: 278,000 IOPS
Endurance: 320 TBW
Warranty: 5 Years
MTBF: 1.5 Million Hours
Drive Writes Per Day (DWPD): 0.3
SLC Write Cache: Yes

Features

TRIM: Yes
SMART: Yes
Power Loss Protection: No
Encryption:
  • Unknown
RGB Lighting: No
PS5 Compatible: No

Notes

NAND Die:

Read Time (tR): Maximum is 50 µs, typical is lower
Typical Program Time (tPROG): 620 µs
Maximum Program Time (tPROG): Maximum is 910 µs
Block Erase Time (tBERS): Maximum is 20 ms, typical is lower
Array Eficiency of over 92%
YMTC 128L Xtacking 2.0 cell architecture consists of two decks connected through deck-interface buffer layer which is the same process with KIOXIA 112L BiCS 3D NAND structure. Cell size, CSL pitch, and 9-hole VC layouts keep the same design and dimension (horizontal/vertical WL and BL pitches) with previous 64L Xtacking 1.0 cell. Total number of gates is 141 (141T) including selectors and dummy WLs for the TLC operation.
This layout has a 1x 4 Plane layout, each one lineup side by side

Oct 4th, 2024 06:56 EDT change timezone

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