The UEFI Forum today announced the release of the Unified Extensible Firmware Interface (UEFI) 2.10 specification and Advanced Configuration and Power Interface (ACPI) 6.5 specification. The new specification versions expand support for new processor types, memory interfaces and platform types, while allowing for crypto agility in post-quantum system security.

"We are excited to share the new Conformance Profiles feature, responsive to community pull for a way to make the UEFI Forum's work useful," said Mark Doran, UEFI Forum President. "The Conformance Profiles feature will expand the platform types UEFI can support to an ever wider range of platform types like IoT, embedded and automotive spaces - beyond general purpose computers."

DeepComputing and Xcalibyte today opened pre-orders for the industry's first native RISC-V development laptop. The hotly anticipated ROMA development platform features an unannounced quad-core RISC-V processor with a companion NPU/GPU for the fastest, seamless RISC-V native software development available.

"Native RISC-V compile is a major milestone," said Mark Himelstein, Chief Technology Officer for RISC-V International. "The ROMA platform will benefit developers who want to test their software running natively on RISC-V. And it should be easy to transfer code developed on this platform to embedded systems."

Headquartered in Aachen and emerging from stealth mode in May, MachineWare is set to revolutionize semiconductor design with its high-speed functional RISC-V simulator, SIM-V. SIM-V, the company's flagship product, combines unprecedented simulation performance with exceptional customizability for applications ranging from the tiniest embedded devices to warehouse-scale supercomputers. SIM-V enables software developers to test full software stacks - including firmware, operating system kernel and complex user-space applications, such as (Java-) virtual machines or rich graphical environments - in real time.

Today's hardware-software systems are becoming increasingly complex, with even tiny edge systems executing millions of lines of code. SIM-V gives software developers the ability to interactively debug even the most complex designs without the need for physical hardware, even before first prototypes are available. Integrating SIM-V into continuous integration systems minimizes test execution times, saves compute resources and allows developers to continue their work sooner.

Imagination Technologies announces IMG RTXM-2200, its first real-time embedded RISC-V CPU, a highly scalable, feature-rich, 32-bit embedded solution with a flexible design for a wide range of high-volume devices. IMG RTXM-2200 is one of the first commercial cores in Imagination's Catapult CPU family, previously announced in December 2021. Accelerating the expansion of its RISC-V offering, Imagination's IMG RTXM-2200 can be integrated into complex SoCs for a range of applications including networking solutions, packet management, storage controllers, and sensor management for AI cameras and smart metering. Together with its market-leading GPU and AI accelerator IP, Imagination's new CPU cores offer customers access to innovative heterogeneous solutions.

This real-time embedded core features up to 128 KB of tightly coupled memories (both instruction and data) for deterministic response and Level 1 cache sizes of up to 128 KB for robust performance. The new CPU offers a range of floating-point formats including single-precision and bfloat16. The latter enables manufacturers to deploy AI applications through this core without the need for an additional chip. This reduces silicon area, for a cost-effective and optimised design in AI cameras and smart metering applications.

SiFive Inc., the founder and leader of RISC-V computing, today announced the release of the latest version of its SiFive Intelligence X280 processor, which introduces significant new features including scalability up to a 16-core cache-coherent complex, WorldGuard trusted protection, and a new interface allowing for seamless integration between the X280 vector unit and customer-designed external AI accelerators or other coprocessors, called VCIX (Vector Coprocessor Interface eXtension). Collectively, these enhanced features deliver unmatched scalability, security, and interoperability to the SiFive X280, the most widely adopted implementation of the RISC-V Vector extension. This latest version of the X280 is a powerful solution for those looking for alternatives to legacy SIMD-style architectures.

Publicly available since April 2021, the SiFive Intelligence X280 has seen rapid adoption as customers gravitate towards its unique combination of performance, power efficiency, and an intuitive programming model. The X280 has claimed double-digit design wins in the past six months alone, in a wide variety of data-driven applications, including AI inference, image processing, datacenter acceleration, and automotive use cases.

Researchers from Università di Bologna and CINECA, the largest supercomputing center in Italy, have been playing with the concept of developing a RISC-V supercomputer. The team has laid the grounds for the first-ever implementation that demonstrates the capability of the relatively novel ISA to run high-performance computing. To create a supercomputer, you need pieces of hardware that seem like Lego building blocks. Those are called clusters, made from a motherboard, processor, memory, and storage. Italian researchers decided to try and use something different than Intel/AMD solution to the problem and use a processor based on RISC-V ISA. Using SiFive's Freedom U740 SoC as the base, researchers named their RISC-V cluster "Monte Cimone."

Monte Cimone features four dual-board servers, each in a 1U form factor. Each board has a SiFive's Freedom U740 SoC with four U74 cores running up to 1.4 GHz and one S7 management core. In total, eight nodes combine for a total of 32 RISC-V cores. Paired with 16 GB of 64-bit DDR4 memory operating at 1866s MT/s, PCIe Gen 3 x8 bus running at 7.8 GB/s, one gigabit Ethernet port, USB 3.2 Gen 1 interfaces, the system is powered by two 250 Watt PSUs to support future expansion and addition of accelerator cards.

During the International Supercomputing Conference on May 31, 2022, in Hamburg, Germany, Jeff McVeigh, vice president and general manager of the Super Compute Group at Intel Corporation, announced Rialto Bridge, Intel's data center graphics processing unit (GPU). Using the same architecture as the Intel data center GPU Ponte Vecchio and combining enhanced tiles with Intel's next process node, Rialto Bridge will offer up to 160 Xe cores, more FLOPs, more I/O bandwidth and higher TDP limits for significantly increased density, performance and efficiency.

"As we embark on the exascale era and sprint towards zettascale, the technology industry's contribution to global carbon emissions is also growing. It has been estimated that by 2030, between 3% and 7% of global energy production will be consumed by data centers, with computing infrastructure being a top driver of new electricity use," said Jeff McVeigh, vice president and general manager of the Super Compute Group at Intel Corporation.

SiFive, Inc., the founder and leader of RISC-V computing, today announced it has raised $175 million in a Series F financing round, valuing the company at over $2.5 billion. The Series F round was led by Coatue Management, a global technology investment firm that invests in companies at all stages - from venture to growth through public markets. SiFive is substantially accelerating the development of the company's RISC-V products, future roadmap, and ecosystem to achieve the unlimited potential that RISC-V has for SiFive's customers and partners.

Founded six years ago by the inventors of RISC-V, SiFive introduced the world to the open standard ISA and transformed the future of compute. Today, RISC-V is firmly established as one of the major global compute platforms, with adoption all around the world, as evidenced by recent industry announcements including the Intel $1B innovation fund, featuring a goal of catalyzing the RISC-V ecosystem. SiFive has design wins with more than 100 customers including several of the world's largest hyperscale companies and 8 of the top 10 semiconductor companies, in applications ranging from automotive, AR/VR, client computing, data center, and intelligent edge.

SiFive, Inc., the founder and leader of RISC-V computing, today announced the company will support Intel Foundry Services (IFS) innovation fund's goal to build innovative new RISC-V computing platforms optimized for Intel process technology. The $1B Intel fund will support the creation of disruptive technologies to address modern computing challenges, with the Intel-SiFive collaboration aiming to extend the RISC-V ecosystem. Compute blocks in future silicon chips, optimized for specific classes of workloads, require a vibrant market of semiconductor IP that is further enabled by SiFive's leading RISC-V processor IP optimized and available to customers of IFS. The open nature of the RISC-V instruction set architecture creates freedom to innovate, with specifications and extensions developed by expert contributors from leaders in the semiconductor industry, research institutions, and academia.

SiFive has partnered with IFS to develop a RISC-V development platform, codenamed "Horse Creek," featuring a multi-core SiFive Performance P550 processor, and implemented on the Intel 4 technology platform, on track for availability in 2022. The "Horse Creek" SoC will enable a new generation of RISC-V developer boards, continuing the tradition of SiFive HiFive boards that have helped drive the growth of the RISC-V ecosystem. To be informed of updates on the "Horse Creek" RISC-V developer board, please register here.

As part of its IDM 2.0 (Integrated Device Manufacturer) plan, Intel has announced it has setup a $1 Billion fund to support early-stage startups and established companies building disruptive technologies for the foundry ecosystem. A collaboration between Intel Capital and Intel Foundry Services (IFS), the move aims to capitalize on what Intel sees as the future of the industry: with a focus on an Open Chiplet platform and Open Interconnect Standard, Intel is looking to enable partners to deploy packaging technologies that bring together multiple ISAs (Instruction Set Architectures) within the same chip. The idea is simple: customers will be looking to mix and match several IPs on their semiconductor designs, taking advantage of different strengths (particularly in the power/performance/area equation) from each.

Foundry customers are rapidly embracing a modular design approach to differentiate their products and accelerate time to market. Intel Foundry Services is well-positioned to lead this major industry inflection. With our new investment fund and open chiplet platform, we can help drive the ecosystem to develop disruptive technologies across the full spectrum of chip architectures.

Pat Gelsinger, Intel CEO

The European High Performance Computing Joint Undertaking (EuroHPC JU) has launched 3 new research and innovation projects. The projects aim to bring the EU and its partners in the EuroHPC JU closer to developing independent microprocessor and HPC technology and advance a sovereign European HPC ecosystem. The European Processor Initiative (EPI SGA2), The European PILOT and the European Pilot for Exascale (EUPEX) are interlinked projects and an important milestone towards a more autonomous European supply chain for digital technologies and specifically HPC.

With joint investments of €140 million from the European Union (EU) and the EuroHPC JU Participating States, the three projects will carry out research and innovation activities to contribute to the overarching goal of securing European autonomy and sovereignty in HPC components and technologies, especially in anticipation of the European exascale supercomputers.

In 2016, NVIDIA announced that the company is working on replacing its Fast Logic Controller processor codenamed Falcon with a new GPU System Processor (GSP) solution based on RISC-V Instruction Set Architecture (ISA). This novel RISC-V processor is codenamed NV-RISCV and has been used as GPU's controller core, coordinating everything in the massive pool of GPU cores. Today, NVIDIA has decided to open this NV-RISCV CPU to a broader spectrum of applications starting with 510.39 drivers. According to the NVIDIA documents, this is only available in the select GPUs for now, mainly data-centric Tesla accelerators.

NVIDIA DocumentsSome GPUs include a GPU System Processor (GSP) which can be used to offload GPU initialization and management tasks. This processor is driven by the firmware file /lib/firmware/nvidia/510.39.01/gsp.bin. A few select products currently use GSP by default, and more products will take advantage of GSP in future driver releases.
Offloading tasks which were traditionally performed by the driver on the CPU can improve performance due to lower latency access to GPU hardware internals.

In recent years, government institutions have been funding the development of home-grown hardware that will power the government infrastructure. This trend was born out of a desire to design chips with no back doors implemented so that no foreign body could monitor the government's processes. Today, Russian company Baikal Electronics managed to boot up the Baikal-S processor with 48 cores based on Arm Instruction Set Architecture (ISA). The processor codenamed BE-S1000 manages to operate 48 cores at a 2.0 GHz base frequency, with a maximum boost of 2.5 GHz clock speed. All of that is achieved at the TDP of 120 Watts, making this design very efficient.

When it comes to some server configurations, the Baikal-S processor run in up to four sockets in a server board. It offers a home-grown RISC-V processor for safe boot and management, so the entire SoC is controlled by a custom design. Baikal Electronics provided some benchmark numbers, which you can see in the slides below. They cover SPEC2006 CPU Integer, Coremark, Whetstone, 7Zip, and HPLinkpack performance. Additionally, the company claims that Baikal-S is in line with Intel Xeon Gold 6148 Skylake design and AMD EPYC 7351 CPU based on Zen1 core. Compared to Huawei's Kunpeng 920, the Baikal-S design provides 0.86x performance.

Imagination Technologies announces Catapult, a RISC-V CPU product line designed from the ground-up for next-generation heterogeneous compute needs. Based on RISC-V, the open-source CPU architecture, which is transforming processor design, Imagination's Catapult CPUs can be configured for performance, efficiency, or balanced profiles, making them suitable for a wide range of markets.

Leveraging Imagination's 20 years of experience in delivering complex IP solutions, the new CPUs are supported by the rapidly expanding open-standard RISC-V ecosystem, which continues to shake up the embedded CPU industry by offering greater choice. Imagination's entry will enable the rapidly expanding RISC-V ecosystem to add a greater range of product offerings, especially for heterogeneous systems. Now customers have an even wider choice of solutions built on the open RISC-V ISA, avoiding lock-in with proprietary architectures.

SiFive, Inc., the founder and leader of RISC-V computing, today announced the availability of the SiFive Performance P650 processor, the new range-topping member of the SiFive Performance family, which is expected to be the fastest licensable RISC-V processor IP core in the market. The SiFive Performance P650 will enable RISC-V designs for performance-demanding application processor markets from data center to edge, automotive, compute, mobile and more.

"SiFive's mission is to answer the semiconductor industry's call for more processor IP choices. SiFive is singularly focused on bringing innovative processor technology based on the RISC-V architecture to market," said Dr. Yunsup Lee, co-founder and CTO, SiFive. "Since the announcement of the Performance Series of RISC-V cores earlier this year, SiFive has continued to push the limits of what was previously possible with RISC-V. The SiFive Performance P650 processor IP represents our commitment towards relentless execution, delivering significant performance improvements in record time. This announcement is the next step towards our long-term vision of bringing RISC-V processors to all performance-hungry applications."

Back in June, SiFive, a company focusing on providing RISC-V-based IP solutions, received an offer for a takeover from Intel. With a value of over two billion dollars, the company's request was on the table to accept. However, according to the latest report from Bloomberg, SiFive declined an offer and aimed to get an initial public offering or get acquired by an even larger vendor. What made the company reject, you might question?

Well, according to sources familiar with the deal, Intel's offer of two billion USD was not enough, and it interrupted the company's ideologies of operation. SiFive management didn't like how Intel would integrate the company in its roadmaps and decided to stay independent. For now, the company is looking to start an initial public offering or get acquired an even larger company that would respect its vision and guidelines, unlike Intel's offer.

With the x86 architecture, large hyperscale cloud providers have been experiencing all sorts of troubles, from high power consumption to the high pricing structure of these processors. Companies like Amazon Web Services (AWS) build their processors based on 3rd party instruction set architecture designs. Today, Alibaba, the Chinese giant, has announced the launch of two processors made in-house to serve everything from edge to central server processing. First in line is the RISC-V-based Xuantie series of processors, which can run anything from AliOS, FreeRTOS, RT-Thread, Linux, Android, etc., to other operating systems as well. These processors are open-source, capable of modest processing capabilities, and designed as IPs that anyone can use. You can check them out on T-Head GitHub repositories here.

The other thing that Alibaba announced is the development of a 128-core custom processor based on the Arm architecture. Called Yitian 710 server SoC, TSMC manufactures it on the company on 5 nm semiconductor node. So far, Alibaba didn't reveal any details about the SoC and what Arm cores are used. However, this signifies that the company seeks technology independence from outside sources and wants to take it all in-house. With custom RISC-V processors for lower-power tasks and custom Arm server CPUs, the whole infrastructure is covered. It is just a matter of time before Alibaba starts to replace x86 makers in full. However, given the significant number of chips that the company needs, it may not happen at any sooner date.

The European Processor Initiative (EPI) https://www.european-processor-initiative.eu/, a project with 28 partners from 10 European countries, with the goal of making EU achieve independence in HPC chip technologies and HPC infrastructure, is proud to announce that EPAC 1.0 RISC-V Test Chip samples were delivered to EPI and initial tests of their operation were successful.

One key segment of EPI activities is to develop and demonstrate fully European-grown processor IPs based on the RISC-V Instruction Set Architecture, providing power-efficient and high-throughput accelerator cores named EPAC (European Processor Accelerators).

Having only recently transitioned its Mac ecosystem to the Arm machine architecture, away from x86-64, Apple is finding itself in a position where it must prepare for an eventuality where NVIDIA withholds cutting-edge development of the Arm IP to itself. The democratized nature of the current Arm IP enables licensees like Apple to stay on the cutting-edge; since its holding company SoftBank does not make chips of its own. Apple is turning its attention to open-source machine architectures such as RISC-V, and reported started foundational work on the architecture that could eventually result in its own high-performance SoCs powering the iPhone, other iOS devices, wearables, and future generations of the Mac.

Tachyum Inc. today announced that it has successfully executed the Linux boot process on the field-programmable gate array (FPGA) prototype of its Prodigy Universal Processor, in 2 months after taking delivery of the IO motherboard from manufacturing. This achievement proves the stability of the Prodigy emulation system and allows the company to move forward with additional testing before advancing to tape out.

Tachyum engineers were able to perform the Linux boot, execute a short user-mode program and shutdown the system on the fully functional FPGA emulation system. Not only does this successful test prove that the basic processor is stable, but interrupts, exceptions, timing, and system-mode transitions are, as well. This is a key milestone, which dramatically reduces risk, as booting and running large and complex pieces of software like Linux reliably on the Tachyum FPGA processor prototype shows that verification and hardware stability are past the most difficult turning point, and it is now obvious that verification and testing should successfully complete in the coming months. Designers are now shifting their attention to debug and verification processes, running hundreds of trillions of test cycles over the next few months, and running large scale user mode applications with compatibility testing to get the processor to production quality.

SiFive, Inc., the industry leader in RISC-V processors and silicon solutions, today announced launched the new SiFive Performance family of processors. The SiFive Performance family debuts with two new processor cores, the P270, SiFive's first Linux capable processor with full support for the RISC-V vector extension v1.0 rc, and the SiFive Performance P550 core, SiFive's highest performance processor to date. The new SiFive Performance P550 delivers a SPECInt 2006 score of 8.65/GHz, making it the highest performance RISC-V processor available today, and comparable to existing proprietary solutions in the application processor space.

"SiFive Performance is a significant milestone in our commitment to deliver a complete, scalable portfolio of RISC-V cores to customers in all markets who are at the vanguard of SOC design and are dissatisfied with the status quo," said Dr. Yunsup Lee, Co-Founder and CTO of SiFive. "These two new products cover new performance points and a wide range of application areas, from efficient vector processors that easily displace yesterday's SIMD architectures, to the bleeding edge that the P550 represents. SiFive is proud to set the standard for RISC-V processing and is ready to deliver these products to customers today."

SiFive, one of the hottest new semiconductor start-ups specializing in performance RISC-V processors, has received an offer for acquisition from Intel, for USD $2 billion, according to a Bloomberg report, citing sources close to the deal. SiFive was last valued at $500 million in 2020, when it was raising funds. SiFive is potentially benefiting from NVIDIA's ongoing acquisition of Arm, as the company has the ingredients to whip up high-performance processors based on the open-standard RISC-V machine architecture. Both SiFive and Intel declined to comment on the Bloomberg story.

Tachyum Inc. today announced that it has taken delivery of an IO motherboard for its Prodigy Universal Processor hardware emulator from manufacturing. This provides the company with a complete system prototype integrating CPU, memory, PCI Express, networking and BMC management subsystems when connected to the previously announced field-programmable gate array (FPGA) emulation system board.

The Tachyum Prodigy FPGA DDR-IO Board connects to the Prodigy FPGA CPU Board to provide memory and IO connectivity for the FPGA-based CPU tiles. The fully functional Prodigy emulation system is now ready for further build out, including Linux boot and incorporation of additional test chips. It is available to customers to perform early testing and software development prior to a full four-socket reference design motherboard, which is expected to be available Q4 2021.

Huawei's HiSilicon subsidiary, which specialized in the design and development of semiconductor devices like processors, has made a big announcement today. A while back, the US government has blacklisted Huawei from using any US-made technology. This has rendered HiSilicon's efforts of building processors based on Arm architecture (ISA) practically useless, as the US sanctions applied to that as well. So, the company had to turn to alternative technologies. Today, HiSilicon has announced the new HiSilicon Hi3861 development board, based on RISC-V architecture. This represents an important step to Huawei's silicon independence, as RISC-V is a free and open-source ISA designed for all kinds of workloads.

While the HiSilicon Hi3861 development board features a low-power Hi3861 chip, it is the company's first attempt at building a RISC-V design. It features a "high-performance 32-bit microprocessor with a maximum operating frequency of 160 MHz". While this may sound very pale in comparison to the traditional HiSilicon products, this chip is used for IoT applications, which don't require much processing power. For tasks that need better processing, HiSilicon will surely develop more powerful designs. This just represents an important starting point, where Huawei's HiSilicon moves away from Arm ISA, and steps into another ISA design and development. This time, with RISC-V, the US government has no control over the ISA, as it is free to use by anyone who pleases, with added benefits of no licensing costs. It is interesting to see where this will lead HiSilicon and what products the company plans to release on the new ISA.

SiFive, Inc., the industry leader in RISC-V processors and silicon solutions, today announced that Tenstorrent, an AI semiconductor and software start-up developing next-generation computers, will license the new SiFive Intelligence X280 processor in its AI training and inference processor. SiFive will deliver more details of its SiFive Intelligence initiative including the SiFive Intelligence X280 processor at the Linley Spring Processor Conference on April 23rd.

Tenstorrent's novel approach to inference and training effectively and efficiently accommodates the exponential growth in the size of machine learning models while offering best-in-class performance.