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ASUS ROG RAIDR Express 240 GB

240 GB
Capacity
SF-2281
Controller
MLC
Flash
PCIe 2.0 x2
Interface
Add-In Card
Form Factor
Front
Back
Back
Package
Tweaktown
Package
PCB Front
Tweaktown
PCB Front
PCB Back
Tweaktown
PCB Back
Flash
Tweaktown
Flash
SSD Controller
Controller
NAND Die
NAND Die
RAID Controller
RAID Controller
The ASUS ROG RAIDR Express was a solid-state drive in the Add-In Card form factor, launched on July 31st, 2013, that is no longer in production. It is only available in the 240 GB capacity listed on this page. With the rest of the system, the ASUS ROG RAIDR Express interfaces using a PCI-Express 2.0 x2 connection. The SSD controller is the SF-2281VB2-SDC Phoenix from LSI SandForce, a DRAM cache is not available. ASUS has installed MLC NAND flash on the ROG RAIDR Express, the flash chips are made by Toshiba. To improve write speeds, a cache is used, so bursts of incoming writes are handled more quickly. The ROG RAIDR Express is rated for sequential read speeds of up to 830 MB/s and 810 MB/s write; random IO reaches 100K IOPS for read and 100K for writes.
At its launch, the SSD was priced at 409 USD. The warranty length is set to five years, which is an excellent warranty period. The TBW rating for the ASUS ROG RAIDR Express 240 GB is unknown.

Solid-State-Drive

Capacity: 240 GB
RAID Config: 2x 120 GB
RAID Levels: RAID-0
Overprovisioning: 32.5 GB / 14.5 %
Production: End-of-life
Released: Jul 31st, 2013
Price at Launch: 409 USD
Part Number: PX2-240GB-BOX
Market: Consumer

Physical

Form Factor: Add-In Card
Interface: PCIe 2.0 x2
Protocol: AHCI
Power Draw: Unknown

Controller

Manufacturer: LSI SandForce
Name: SF-2281VB2-SDC Phoenix
Architecture: Tensilica Diamond Standard 32-bit 108Mini
Core Count: Single-Core
Foundry: TSMC
Process: 65 nm
Flash Channels: 8 @ 166 MT/s

RAID Controller

Manufacturer: Marvell
Name: 88SE9230
Architecture: ARM 32-bit Cortex
Core Count: Single-Core

NAND Flash

Manufacturer: Toshiba
Name: A19
Part Number: TH58TEG7DDJBA4C
Type: MLC
Technology: Planar
Speed: 200 MT/s .. 400 MT/s
Capacity: 8 chips @ 128 Gbit
Toggle: 1.0
Topology: Charge Trap
Process: 19 nm
Die Size: 113 mm²
(0.6 Gbit/mm²)
Dies per Chip: 2 dies @ 64 Gbit
Planes per Die: 2
Program Time (tProg): 1100 µs
Die Write Speed: 15 MB/s
Page Size: 16 KB
Block Size: 256 Pages
Plane Size: 2132 Blocks

DRAM Cache

Type: None

Performance

Sequential Read: 830 MB/s
Sequential Write: 810 MB/s
Random Read: 100,000 IOPS
Random Write: 100,000 IOPS
Endurance: Unknown (per SSD)
Warranty: 5 Years
MTBF: 0.6 Million Hours
SLC Write Cache: Unknown

Features

TRIM: Yes
SMART: Yes
Power Loss Protection: No
Encryption:
  • AES-128
RGB Lighting: No
PS5 Compatible: No

Reviews

Notes

Drive:

Each SSD has 8 NAND Flash Packages with 16 packages in total

Controller:

It's a newer revision of the VB1 controller but with a reduced power consumption
The Diamond Standard 108Mini is a fully synthesizable 32-bit RISC controller core. It is a small, cache-less RISC controller with tightly-coupled local instruction and data memories, a rich interrupt architecture, and high arithmetic and DSP performance. The Diamond 108Mini features low-power consumption for portable applications. Although the Diamond 108Mini is smaller in die area, its performance is 1.34 Dhrystone MIPS/MHz at 420 MHz in a 90nm G process. It also achieves high performance on DSP applications and engine and motor control applications because of the built-in 32x32 multiplier and 32-bit integer divider.

The Diamond 108Mini delivers fast and flexible interrupt handling with the availability of low interrupt latency and a rich interrupt architecture. The processor has deterministic behavior for applications with hard real-time constraints. 32 base registers are windowed 16 at a time, which enables faster context switching due to reduced stack operations. Local single-cycle SRAM allows time critical code to be placed near the CPU. Dual local data SRAM enables the processor access to one bank of RAM while an external DNA operation can operate on the other bank. Separate instruction and data memory interfaces lead to lower contention than unified interface architectures.
Jun 1st, 2024 18:23 EDT change timezone

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