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Dera D7436 1.9 TB

1.9 TB
Capacity
EMEI
Controller
TLC
Flash
PCIe 4.0 x4
Interface
U.2
Form Factor
Front
SSD Controller
Controller
NAND Die
NAND Die
The Dera D7436 is a solid-state drive in the U.2 form factor. It is available in capacities ranging from 1.9 TB to 15 TB. This page reports specifications for the 1.9 TB variant. With the rest of the system, the Dera D7436 interfaces using a PCI-Express 4.0 x4 connection. The SSD controller is the EMEI 7603-A0 from Dera, a DRAM cache chip is available. Dera has installed 128-layer TLC NAND flash on the D7436, the flash chips are made by YMTC. Thanks to support for the fast PCI-Express 4.0 interface, performance is excellent. The D7436 is rated for sequential read speeds of up to 7,100 MB/s and 4,800 MB/s write; random IO reaches 1600K IOPS for read and 270K for writes.
The SSD's price at launch is unknown. The warranty length is set to five years, which is an excellent warranty period. Dera guarantees an endurance rating of 3504 TBW, a high value.

Solid-State-Drive

Capacity: 1.9 TB (1920 GB)
Variants: 1.9 TB 3.8 TB 7.5 TB 15 TB
Overprovisioning: 259.9 GB / 14.5 %
Production: Active
Released: Unknown
Part Number: DERAP44YGR01T9US
Market: Enterprise

Physical

Form Factor: U.2
Interface: PCIe 4.0 x4
Protocol: NVMe 2.0
Power Draw: 6.0 W (Idle)
Unknown (Avg)
18.5 W (Max)

Controller

Manufacturer: Dera
Name: EMEI 7603-A0
Architecture: ARM
Foundry: TSMC FinFET
Process: 12 nm
Flash Channels: 16 @ 1,200 MT/s
Chip Enables: 8
Controller Features: DRAM (enabled)

NAND Flash

Manufacturer: YMTC
Name: Xtacking 2.0 (CDT1B)
Type: TLC
Technology: 128-layer
Speed: 1600 MT/s
Capacity: Unknown
ONFI: 4.1
Topology: Charge Trap
Die Size: 60 mm²
(8.5 Gbit/mm²)
Planes per Die: 4
Decks per Die: 2
Word Lines: 141 per NAND String
90.8% Vertical Efficiency
Read Time (tR): 50 µs
Program Time (tProg): 620 µs
Block Erase Time (tBERS): 20 ms
Die Read Speed: 1280 MB/s
Die Write Speed: 70 MB/s
Endurance:
(up to)		 3000 P/E Cycles
Page Size: 16 KB
Block Size: 2304 Pages
Plane Size: 1980 Blocks

DRAM Cache

Type: DDR3
Capacity: Unknown

Performance

Sequential Read: 7,100 MB/s
Sequential Write: 4,800 MB/s
Random Read: 1,600,000 IOPS
Random Write: 270,000 IOPS
Endurance: 3504 TBW
Warranty: 5 Years
Drive Writes Per Day (DWPD): 1.0
Write Cache: N/A

Features

TRIM: Yes
SMART: Yes
Power Loss Protection: Yes
Encryption:
  • AES-256
RGB Lighting: No
PS5 Compatible: No

Notes

NAND Die:

Read Time (tR): Maximum is 50 µs, typical is lower
Typical Program Time (tPROG): 620 µs
Maximum Program Time (tPROG): Maximum is 910 µs
Block Erase Time (tBERS): Maximum is 20 ms, typical is lower
Array Eficiency of over 92%
YMTC 128L Xtacking 2.0 cell architecture consists of two decks connected through deck-interface buffer layer which is the same process with KIOXIA 112L BiCS 3D NAND structure. Cell size, CSL pitch, and 9-hole VC layouts keep the same design and dimension (horizontal/vertical WL and BL pitches) with previous 64L Xtacking 1.0 cell. Total number of gates is 141 (141T) including selectors and dummy WLs for the TLC operation.
This layout has a 1x 4 Plane layout, each one lineup side by side
Jun 1st, 2024 18:32 EDT change timezone

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