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Kingston DC500R 7.5 TB

7.5 TB
Capacity
Phison S12
Controller
TLC
Flash
SATA 6 Gbps
Interface
2.5"
Form Factor
Package
Package
SSD Controller
Controller
NAND Die
NAND Die
The Kingston DC500R is a solid-state drive in the 2.5" form factor, launched on May 4th, 2019. It is available in capacities ranging from 480 GB to 7.5 TB. This page reports specifications for the 7.5 TB variant. With the rest of the system, the Kingston DC500R interfaces using a SATA 6 Gbps connection. The SSD controller is the PS3112-S12-27 from Phison, a DRAM cache chip is available. Kingston has installed 64-layer TLC NAND flash on the DC500R, the flash chips are made by Micron. To improve write speeds, a pseudo-SLC cache is used, so bursts of incoming writes are absorbed more quickly. The DC500R is rated for sequential read speeds of up to 555 MB/s and 525 MB/s write.
At its launch, the SSD was priced at 1467 USD. The warranty length is set to five years, which is an excellent warranty period. The TBW rating for the Kingston DC500R 7.5 TB is unknown.

Solid-State-Drive

Capacity: 7.5 TB (7680 GB)
Variants: 480 GB 960 GB 1.9 TB 3.8 TB 7.5 TB
Overprovisioning: 1039.4 GB / 14.5 %
Production: Active
Released: May 4th, 2019
Price at Launch: 1467 USD
Part Number: SEDC500R/7680G
Market: Enterprise

Physical

Form Factor: 2.5"
Interface: SATA 6 Gbps
Protocol: AHCI
Power Draw: 1.6 W (Idle)
1.6 W (Avg)
7.5 W (Max)

Controller

Manufacturer: Phison
Name: PS3112-S12-27
Architecture: ARM 32-bit
Core Count: Quad-Core
Frequency: 666 MHz
Foundry: TSMC
Process: 28 nm
Flash Channels: 8 @ 667 MT/s
Chip Enables: 4
Controller Features: DRAM (enabled)

NAND Flash

Manufacturer: Micron
Name: B17A FortisFlash
Type: TLC
Technology: 64-layer
Speed: 50 MT/s .. 667 MT/s
Capacity: 16 chips @ 4 Tbit
ONFI: 4.0
Topology: Floating Gate
Process: 16 nm
Die Size: 108 mm²
(4.7 Gbit/mm²)
Dies per Chip: 8 dies @ 512 Gbit
Planes per Die: 4
Decks per Die: 2
Word Lines: 74 per NAND String
86.5% Vertical Efficiency
Read Time (tR): 88 µs
Program Time (tProg): 930 µs
Block Erase Time (tBERS): 15 ms
Die Read Speed: 727 MB/s
Die Write Speed: 69 MB/s
Endurance:
(up to)
3000 P/E Cycles
(40000 in SLC Mode)
Page Size: 16 KB
Block Size: 2304 Pages
Plane Size: 504 Blocks

DRAM Cache

Type: DDR4-2666 CL19
Name: Micron MT40A1G8SA-075:E
Capacity: 8192 MB
(4x 2048 MB)
Organization: 16Gx8

Performance

Sequential Read: 555 MB/s
Sequential Write: 525 MB/s
Random Read: 98,000 IOPS
Random Write: Unknown
Endurance: Unknown
Warranty: 5 Years
MTBF: 2.0 Million Hours
SLC Write Cache: Yes

Features

TRIM: Yes
SMART: Yes
Power Loss Protection: Yes
Encryption:
  • AES-256
  • TCG Opal
RGB Lighting: No
PS5 Compatible: No

Notes

Drive:

Make use of a bunch of Tantalum Capacitors for PLP circuit

Controller:

2 main cores using Cortex-R5 clocked at 666 MHz with CoXProcessor technology (one additional dual-core) Cortex-R5 clocked at a lower clock for better efficience.

NAND Die:

tPROG with some Overhead: ~ 930µs (Avg)
Effective Program page time without VPP : 1900μs(TYP) ( ~ 33 MB/s)

Jun 1st, 2024 15:55 EDT change timezone

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