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MiWhole CT100 512 GB

512 GB
Capacity
MAP1202A-F1C
Controller
TLC
Flash
PCIe 3.0 x4
Interface
M.2 2280
Form Factor
PCB Front
PCB Front
SSD Controller
Controller
NAND Die
NAND Die
The MiWhole CT100 is a solid-state drive in the M.2 2280 form factor. It is available in capacities ranging from 512 GB to 2 TB. This page reports specifications for the 512 GB variant. With the rest of the system, the MiWhole CT100 interfaces using a PCI-Express 3.0 x4 connection. The SSD controller is the MAP1202A-F1C Cougar from MaxioTech, a DRAM cache is not available. MiWhole has installed 128-layer TLC NAND flash on the CT100, the flash chips are made by YMTC. To improve write speeds, a pseudo-SLC cache is used, so bursts of incoming writes are absorbed more quickly. The CT100 is rated for sequential read speeds of up to 3,554 MB/s and 1,853 MB/s write; random IO reaches 250K IOPS for read and 327K for writes.
At its launch, the SSD was priced at 37 USD. The warranty length is set to three years, which is above average, but shorter than the five years offered by many other vendors. MiWhole guarantees an endurance rating of 224 TBW, a typical value for consumer SSDs.

Solid-State-Drive

Capacity: 512 GB
Variants: 512 GB 1 TB 2 TB
Overprovisioning: 35.2 GB / 7.4 %
Production: Active
Released: Unknown
Price at Launch: 37 USD
Part Number: M-SSD-CT100-512GB
Market: Consumer

Physical

Form Factor: M.2 2280 (Single-Sided)
Interface: PCIe 3.0 x4
Protocol: NVMe 1.3
Power Draw: Unknown (Idle)
Unknown (Avg)
3.0 W (Max)

Controller

Manufacturer: MaxioTech
Name: MAP1202A-F1C Cougar
Architecture: ARM Cortex-R5
Core Count: Dual-Core
Foundry: TSMC
Process: 22 nm
Flash Channels: 4 @ 1,600 MT/s
Chip Enables: 4
Controller Features: HMB (enabled)

NAND Flash

Manufacturer: YMTC
Name: Xtacking 2.0 (CDT1B)
Part Number: YMC3G001Tb62BA1C0
Type: TLC
Technology: 128-layer
Speed: 1600 MT/s
Capacity: 4 chips @ 1 Tbit
ONFI: 4.1
Topology: Charge Trap
Die Size: 60 mm²
(8.5 Gbit/mm²)
Dies per Chip: 2 dies @ 512 Gbit
Planes per Die: 4
Decks per Die: 2
Word Lines: 141 per NAND String
90.8% Vertical Efficiency
Read Time (tR): 50 µs
Program Time (tProg): 620 µs
Block Erase Time (tBERS): 20 ms
Die Read Speed: 1280 MB/s
Die Write Speed: 70 MB/s
Endurance:
(up to)
3000 P/E Cycles
Page Size: 16 KB
Block Size: 2304 Pages
Plane Size: 1980 Blocks

DRAM Cache

Type: None
Host-Memory-Buffer (HMB): 32 MB

Performance

Sequential Read: 3,554 MB/s
Sequential Write: 1,853 MB/s
Random Read: 250,000 IOPS
Random Write: 327,000 IOPS
Endurance: 224 TBW
Warranty: 3 Years
MTBF: 1.5 Million Hours
Drive Writes Per Day (DWPD): 0.4
SLC Write Cache: Yes

Features

TRIM: Yes
SMART: Yes
Power Loss Protection: No
Encryption:
  • Unknown
RGB Lighting: No
PS5 Compatible: No

Same Drive

This section lists other SSDs in our database using the exact same hardware components

Notes

NAND Die:

Read Time (tR): Maximum is 50 µs, typical is lower
Typical Program Time (tPROG): 620 µs
Maximum Program Time (tPROG): Maximum is 910 µs
Block Erase Time (tBERS): Maximum is 20 ms, typical is lower
Array Eficiency of over 92%
YMTC 128L Xtacking 2.0 cell architecture consists of two decks connected through deck-interface buffer layer which is the same process with KIOXIA 112L BiCS 3D NAND structure. Cell size, CSL pitch, and 9-hole VC layouts keep the same design and dimension (horizontal/vertical WL and BL pitches) with previous 64L Xtacking 1.0 cell. Total number of gates is 141 (141T) including selectors and dummy WLs for the TLC operation.
This layout has a 1x 4 Plane layout, each one lineup side by side

Jun 1st, 2024 16:23 EDT change timezone

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