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Solidigm P5430 31 TB

31 TB
Capacity
Unknown
Controller
pQLC (PLC)
Flash
PCIe 4.0 x4
Interface
U.2
Form Factor
Front
NAND Die
NAND Die
The Solidigm P5430 is a solid-state drive in the U.2 form factor, launched on May 16th, 2023. It is only available in the 31 TB capacity listed on this page. With the rest of the system, the Solidigm P5430 interfaces using a PCI-Express 4.0 x4 connection. The actual SSD controller chip used it unknown, we'll update this page when we find out more. . Solidigm has installed 192-layer pQLC (PLC) NAND flash on the P5430, the flash chips are made by Intel. Thanks to support for the fast PCI-Express 4.0 interface, performance is excellent. The P5430 is rated for sequential read speeds of up to 7,000 MB/s and 3,000 MB/s write; random IOPS reach up to 971K for reads and 120K for writes.
The SSD's price at launch is unknown. The warranty length is set to five years, which is an excellent warranty period. Solidigm guarantees an endurance rating of 102597 TBW, a high value.

Solid-State-Drive

Capacity: 31 TB (30720 GB)
Overprovisioning: Unknown
Production: Active
Released: May 16th, 2023
Part Number: Unknown
Market: Consumer

Physical

Form Factor: U.2
Interface: PCIe 4.0 x4
Protocol: NVMe 1.4
Power Draw: Unknown

Controller

Model: Unknown

NAND Flash

Manufacturer: Intel
Name: N4PA Q5171A
Type: pQLC (PLC)
Technology: 192-layer
Speed: 1600 MT/s
Capacity: Unknown
Topology: Floating Gate
Die Size: 73 mm²
(18.2 Gbit/mm²)
Planes per Die: 4
Decks per Die: 4
Endurance:
(up to)		 3000 P/E Cycles
(250000 in SLC Mode)
Page Size: 16 KB

DRAM Cache

Type and Size: Unknown

Performance

Sequential Read: 7,000 MB/s
Sequential Write: 3,000 MB/s
Random Read: 971,000 IOPS
Random Write: 120,000 IOPS
Endurance: 102597 TBW
Warranty: 5 Years
Drive Writes Per Day (DWPD): 1.8
Write Cache: N/A
Endurance - DWPD:32517 TBW
DWPD - Random:0.58

Features

TRIM: Yes
SMART: Yes
Power Loss Protection: Yes
Encryption:
  • Unknown
RGB Lighting: No
PS5 Compatible: No

Notes

Drive:

Endurance at 100% 4KB Random Write - 32517 TB (0.58DWPD)

NAND Die:

Die read speed: aproximation
Die write speed: aproximation
In order to enable a balanced Gray data encoding, all five pages of data are needed in
both the first and second pass of the program algorithm. While this is the norm for most
QLC implementations except [1], it requires the storage of a few megabytes of data per
die in a DRAM or similar media. Instead, we use a 1b/cell (SLC) cache on the NAND die
to store the data needed for the two-pass PLC programming algorithm. To keep the area
overhead of the SLC cache to less than 2%, we improved the SLC reliability to 250k
program/erase (P/E) cycles, commensurate with 1k of P/E cycle capability in the present
PLC work.
Jun 1st, 2024 15:37 EDT change timezone

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