_33
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- Joined
- Mar 25, 2006
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| System Name | BEAST |
|---|---|
| Processor | Intel Core i7 920 C0 Quad Core Processor LGA1366 2.66GHZ Bloomfield 8MB LGA batch 3844A509 |
| Motherboard | ASUS P6T Deluxe V2 X58 ATX LGA1366 DDR3 |
| Cooling | CoolIt ECO A.L.C. 120mm radiator |
| Memory | G.SKILL F3-12800CL8TU-6GBPI PC3-12800 6GB 3X2GB DDR3-1600 CL8-8-8-21 |
| Video Card(s) | Sapphire Radeon HD 4890 1GB 850MHZ 1GB 3.9GHZ GDDR5 PCI-E 2XDVI HDTV |
| Storage | SAMSUNG SPINPOINT F1 750GB X 2, WD2500KS 250GB, WD15EARS 1.5TB, WD20EARS 2.0TB |
| Display(s) | LG W2361V-PF Monitors 23” Widescreen LCD Monitor (23.0” diagonal) |
| Case | Cooler Master CM 690 II Advanced |
| Power Supply | Thermaltake Toughpower 600W Power Supply ATX V2.2 20/24PIN EPS12V Qfan 140MM Fan Active PFC |
| Software | Windows 7 Pro 64bit |
ROADMAP
Here's a nice one!
And INQ rumours and more rumours
The K8L 4X4 approach official AMD info
Hyper Transport 3 (HT3) rumours from France
Some AMD slides
From Dailytech
AMD keynotes resumed
Article at Pure Overclock on K8L
* K8 revision F has 3 complex decoders, the rev G will have 4 (like Conroe)
* 32 bytes prefetch (instead of 16 bytes on K8-F), an obvious step with the added SSE number crunching power.
* OOO, or out-of-order L2 read/write buffer that expedites data neeeded for execution, equipped with an out-of-order load/store buffer (duh!)
* 65nm SOI (we knew that, didn't we?)
* Pacifica virtualization
* Presidio
* Possibility of integrating a co-processor
* Surprisingly robust DDR-2 controller with an improved Crossbar and Arbitrator (???)
* Everything else looks the same though, which means the same 3 INT, 3 AGU, and most importantly the same 3 FPU/SSE units which can deliver 2 x 64 bit results per clock cycle peak (*** This seems totally wrong ***)
* It has a shared expandable L3 cache
* Quad Core capability
* Per core voltage control
* The new core will support 48-bit addressing and 1GB pages
* Hyper Transport 3.0 (4x 16 bit links instead of 3 x 16 bit, which will give 2.6 Ghz and up to 41.6 GB/s bandwidth as opposed to 1.4Ghz and 22.4 GB/s on HT2)
* DICE (Dynamic Independent Core Engagement): Enables cores to be independently managed to save energy / heat dissimation, next step from Cool 'n' Quiet (?)).
* DDR3 is in the wings when the spec 'settles down' (support for DDR3 ?)
* RAS, another area where AMD is sorely lacking. It is addressing the major sore points with support for memory mirroring, data poisoning support, and HT retry.
* It is doing the obvious doubling of SSE/FP resources, old news now (meaning 128 bit instead of 64 bit, AMD says DOUBLING of the FPU calculation power)
* Added instructions; starting with the bit manipulation instructions LZCNT and POPCNT. It also added SSE extensions EXTRQ/INSERTQ and MOVNTSD/MOVNTSS. No word on SSE4 though.
Here's a nice one!
And INQ rumours and more rumours
The K8L 4X4 approach official AMD info
Hyper Transport 3 (HT3) rumours from France
Some AMD slides
From Dailytech
AMD keynotes resumed
Article at Pure Overclock on K8L
* K8 revision F has 3 complex decoders, the rev G will have 4 (like Conroe)
* 32 bytes prefetch (instead of 16 bytes on K8-F), an obvious step with the added SSE number crunching power.
* OOO, or out-of-order L2 read/write buffer that expedites data neeeded for execution, equipped with an out-of-order load/store buffer (duh!)
* 65nm SOI (we knew that, didn't we?)
* Pacifica virtualization
* Presidio
* Possibility of integrating a co-processor
* Surprisingly robust DDR-2 controller with an improved Crossbar and Arbitrator (???)
* Everything else looks the same though, which means the same 3 INT, 3 AGU, and most importantly the same 3 FPU/SSE units which can deliver 2 x 64 bit results per clock cycle peak (*** This seems totally wrong ***)
* It has a shared expandable L3 cache
* Quad Core capability
* Per core voltage control
* The new core will support 48-bit addressing and 1GB pages
* Hyper Transport 3.0 (4x 16 bit links instead of 3 x 16 bit, which will give 2.6 Ghz and up to 41.6 GB/s bandwidth as opposed to 1.4Ghz and 22.4 GB/s on HT2)
* DICE (Dynamic Independent Core Engagement): Enables cores to be independently managed to save energy / heat dissimation, next step from Cool 'n' Quiet (?)).
* DDR3 is in the wings when the spec 'settles down' (support for DDR3 ?)
* RAS, another area where AMD is sorely lacking. It is addressing the major sore points with support for memory mirroring, data poisoning support, and HT retry.
* It is doing the obvious doubling of SSE/FP resources, old news now (meaning 128 bit instead of 64 bit, AMD says DOUBLING of the FPU calculation power)
* Added instructions; starting with the bit manipulation instructions LZCNT and POPCNT. It also added SSE extensions EXTRQ/INSERTQ and MOVNTSD/MOVNTSS. No word on SSE4 though.
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