Are All GHZ Created Equal on CPU's in Gaming

[ZweiGaming]

i do agree isnt going with skylake a good idea just for the possibility of something coming out in skylake that will be great or better... I plan on buying everything on either black Friday or cyber Monday

 

[GorbazTheDragon]

Yeah, with a bit of luck the supply will have smoothed out by then.

Wow, just checked, already dropped by 20 USD from wednesday...

 

[BarbaricSoul]

i do agree isnt going with skylake a good idea just for the possibility of something coming out in skylake that will be great or better...

I wouldn't bet on it. Going by history, at the most, Intel will release a version of the 6700k with a slithly higher clock speed (2600k-2700k, 4770k-4790k) or they'll release a newer chipset with a slitghly better CPU archtecture (2700K-3770K). None of which offered enough boosts in performance to justify the upgrade costs. Same reason I'm still running a 3930K. I'm thinking the next generation may be just enough performance gain to justify me upgrading. X99 platforms don't offer that IMHO.

 

[Schmuckley]

Short answer:No
Longer answer: No,bcuz IPC,Cache sizes/speeds,and RAM latency.

 

[ZweiGaming]

well to be fair i would be saving $100-$200 by going with a 4790k and be getting the relative same performance

 

[R-T-B]

I'm not sure I'd recomend a 4790k at this point, but I'm a "gotta-have-the-latest" nut.

Ram latency on DDR4 isn't actually bad, it's actually often better on a CL/Mhz ratio.

And Skylake has the highest IPC of anything to date per core.

That said, the IPC dips if you don't get high Mhz ram. It seems to like that. I recomend at least DDR4-2800 and you can tune from that to a lower rating of 2666 if your IMC (integrated memory controller) gives you fits, but it usually doesn't.

Haswell-E is also interesting if you can afford it.

 

[ZweiGaming]

I'm not sure I'd recomend a 4790k at this point, but I'm a "gotta-have-the-latest" nut.

Ram latency on DDR4 isn't actually bad, it's actually often better on a CL/Mhz ratio.

And Skylake has the highest IPC of anything to date per core.

That said, the IPC dips if you don't get high Mhz ram. It seems to like that. I recomend at least DDR4-2800 and you can tune from that to a lower rating of 2666 if your IMC (integrated memory controller) gives you fits, but it usually doesn't.

Haswell-E is also interesting if you can afford it.

but thats throwing another $200ish dollars i dont have

 

[EarthDog]

How would IPC dip because of RAM? RAM isn't a bottleneck. IPC is IPC is IPC (for all intents and purposes).

No 66/6700K will give yo fits with 2800Mhz... None (unless the IMC is bad).

 

[R-T-B]

How would IPC dip because of RAM? RAM isn't a bottleneck. IPC is IPC is IPC (for all intents and purposes).

No 66/6700K will give yo fits with 2800Mhz... None (unless the IMC is bad).

It's just what I read. I never had one give me fits that was just regurgitated info. I think it was mostly an issue with early BIOS more than anything.

I did notice that for whatever reason, skylake does seem to dip in performance at lower ram mhz on my board, but it could be isolated.

You are of course correct that that's not IPC, you'll have to grant me that error, it's early here.

 

[Frag_Maniac]

but thats throwing another $200ish dollars i dont have

Exactly, there's been so many tests on the 6000 series CPUs and DDR4 indicating no performance increase to make it pointless really. The only thing you're really getting with Skylake is a slightly better chipset.

It's a solid reason to wait and see how good Zen will be if you have an adequate sys to play on until then. DDR4 should drop in price more by then too, and we'll likely see a better selection of lower CAS modules too.

This is what I'm doing, and every time I mention it, I find others are too. There are a LOT of people upset with Intel's complacency.

 

[R-T-B]

Exactly, there's been so many tests on the 6000 series CPUs and DDR4 indicating no performance increase to make it pointless really. The only thing you're really getting with Skylake is a slightly better chipset.

It's a solid reason to wait and see how good Zen will be if you have an adequate sys to play on until then. DDR4 should drop in price more by then too, and we'll likely see a better selection of lower CAS modules too.

This is what I'm doing, and every time I mention it, I find others are too. There are a LOT of people upset with Intel's complacency.

Oh god yes, if we are talking economic bang for your buck Skylake and Haswell-E isn't economical until ram prices come down at least. Sorry, I was only half awake earlier this morning with my advice... happens to the best of us at times.

 

[Schmuckley]

How would IPC dip because of RAM? RAM isn't a bottleneck. IPC is IPC is IPC (for all intents and purposes).

No 66/6700K will give yo fits with 2800Mhz... None (unless the IMC is bad).

IPS can be affected by RAM speed/latency.
RAM is a bottleneck.

 

[Mussels]

IPS can be affected by RAM speed/latency.
RAM is a bottleneck.

ram *CAN BE* a bottleneck. not is, which implies always.

 

[R-T-B]

IPC is instructions per clock, and unless something is terribly wrong, it should be pulling instructions from the local onboard cache for instructions in L1, not from ram. So no, not really.

Net performance per clock would be a better way to describe something that is effected by ram, in my understanding.

 

[Aquinus]

IPC is instructions per clock, and unless something is terribly wrong, it should be pulling instructions from the local onboard cache for instructions in L1, not from ram. So no, not really.

Net performance per clock would be a better way to describe something that is effected by ram, in my understanding.

Depends on the size of the application. Intel does a damn good job at caching data so I'm willing to bet cache hits occur a lot more often than you think, even under regular operation. It also doesn't have to come from L1 instruction or data cache, it could reside in L2 or L3 a lot of cache schemes will write-back or write-thru cache, which means that it will work its way synchronously or asynchronously through the memory hierarchy until permanent storage is written to.

IPC can be impacted my memory speed but, caching mitigates that case pretty well and high memory speeds practically eliminates it. Modern CPUs don't tend to easily get starved for memory bandwidth.

 

[BiggieShady]

Depends on the size of the application.

Yes, but given how huge cpu caches are nowdays, I'd say it depends more on the type of application ... one extreme example is a memtest application - it doesn't reuse data, just reads and writes all RAM cells sequentially and once per pass ... cache would serve here for latency hiding only, but in this scenario it can only mitigate lower ram bandwidth in short bursts (each burst followed by long waiting for RAM).

 

[Aquinus]

Yes, but given how huge cpu caches are nowdays, I'd say it depends more on the type of application ... one extreme example is a memtest application - it doesn't reuse data, just reads and writes all RAM cells sequentially and once per pass ... cache would serve here for latency hiding only, but in this scenario it can only mitigate lower ram bandwidth in short bursts (each burst followed by long waiting for RAM).

You're half right. The data being read from memory by the application might be different but you know what isn't? The application code itself which is stored in memory and is cacheable. Instructions are going to get cached more than the data will under that kind of workload. In fact, memory tests are so basic, the entire application probably can fit into cache and since it's being accessed a lot more often than any given memory location, it will stay in cache. If you're scanning all of memory space, all of that is going to get kicked out of cache quickly because it's never reused whereas the application itself will constantly be looping over each section of memory. Simply put, there is a speed up, it's just not from accessing data from the application. Just wanted to make that clear because your comment seems to insinuate that cache is ineffective because of such workload which isn't true. Sure, it may be less effective but, the speed up is just from the application code, not memory accesses themselves for a scan. A cache doesn't do you any good if you're reading all of memory sequentially, that's not why it exists.

 

[BiggieShady]

Just wanted to make that clear because your comment seems to insinuate that cache is ineffective because of such workload which isn't true.

Ah, didn't mean to insinuate that ... less effective not ineffective. I was assuming that all instructions are indeed cached in this special case, and was thinking of data only - in retrospect, following the chain of replies, I see where the implication comes from since the discussion started on RAM speed affecting cpu's IPC.

Sure, it may be less effective but, the speed up is just from the application code, not memory accesses themselves for a scan. A cache doesn't do you any good if you're reading all of memory sequentially, that's not why it exists.

Bolded part is exactly the reason I picked that example (and called it extreme) to point out how type of application matters. Of course memtest is not written to make optimal use of cache, but rather to test RAM.
Now, question is to what extent it matters for the IPC, since super scalar processors are doing other instructions while waiting for memory controller or cache (and multiples of them per clock if they are mutually non-dependant) ... that would depend how many memory read/write instructions are in comparison to ALU/FPU instructions in total ... also the reason I was talking about memtest (lots of memory reads/writes, and almost no compute).
Just to be clear, I do agree that if instructions (or at least performance critical sections) can't fit in the cache, that takes the greatest toll for the IPC - having to get them from RAM. Let's just say I'm thankful for cache hierarchy ... and also curious how Broadwells with L4 eDram cache fare in that regard.

 

[Aquinus]

Now, question is to what extent it matters for the IPC, since super scalar processors are doing other instructions while waiting for memory controller or cache (and multiples of them per clock if they are mutually non-dependant) ... that would depend how many memory read/write instructions are in comparison to ALU/FPU instructions in total ... also the reason I was talking about memtest (lots of memory reads/writes, and almost no compute).

Ah yes. The pipeline would probably get held up on FETCH and STORE operations in cases like memtest86. Super scalar CPUs are great when you're not running the same operation over and over again or doing strange, unpredictable branches. Branch mispredictions is what hurts the most since it stalls the entire pipeline and needs to start execution over from right after the mispredicted branch. That's actually a big reason why the Pentium 4 and netburst sucked and why Bulldozer's IPC was meh. Long pipelines suffer badly when stalls occur but, I digress.

also curious how Broadwells with L4 eDram cache fare in that regard.

I thought that the eDRAM last level cache is just for the iGPU and isn't used for your standard run of the mill CPU cores. I'm pretty sure that's how it works on the 4770HQ in my laptop for work. I'm actually surprised at how well the Iris Pro handles itself.

 

[BiggieShady]

Branch mispredictions is what hurts the most since it stalls the entire pipeline and needs to start execution over from right after the mispredicted branch. That's actually a big reason why the Pentium 4 and netburst sucked and why Bulldozer's IPC was meh.

Damn right about branch misprediction and yes you do tend to digress but thankfully we help our cpus by avoiding complex nested conditional statements because we see them as bad coding

I thought that the eDRAM last level cache is just for the iGPU and isn't used for your standard run of the mill CPU cores. I'm pretty sure that's how it works on the 4770HQ in my laptop for work.

That's what I thought but I saw at pcper's skylake (p)review some benching results that indicate otherwise ... there was only one benchmark demanding enough that showed 5775C as faster than skylake (probably due to L4 eDram) ... let me try to find that and link it here ...

http://www.pcper.com/reviews/Proces...ke-First-Enthusiasts/Rendering-and-Scientific

While the Skylake scores in Euler3D are great to see, great single threaded results, better four threaded performance than Haswell-E and better overall performance the Haswell, the Broadwell scores stand out to me. Despite the several hundred MHz deficit in clock speed, the Core i7-5775C is actually the fastest device at 2-thread and 4-thread results and bests Skylake the rest of the way. Clearly that large eDRAM cache is useful for other purposes than just gaming!

 

[ZweiGaming]

does anyone know a good micro atx case that could fit a r9 390 or do i have to jump up to a mid tower case

 

[BarbaricSoul]

http://pcpartpicker.com/part/cooler-master-case-nse200kkn1

 

[ZweiGaming]

http://pcpartpicker.com/part/cooler-master-case-nse200kkn1

i seen that one but i kinda liked either the bitfenix Prodigy M or the Phenom i just had no clue if i could fit a R9 390 in them

 

[BarbaricSoul]

i seen that one but i kinda liked either the bitfenix Prodigy M or the Phenom i just had no clue if i could fit a R9 390 in them

either one of those cases will hold the R9 390. You may have to remove some of the extra drive racks of the Prodigy, but both cases support video cards of 12.6" in length. The R9 390 cards are 11-12" in length.

 

[ZweiGaming]

either one of those cases will hold the R9 390. You may have to remove some of the extra drive racks of the Prodigy, but both cases support video cards of 12.6" in length. The R9 390 cards are 11-12" in length.

Thank you so much good sir