Friday, June 16th 2006
Intel Set to Integrate Memory, Graphics Controllers into Microprocessors.
Intel Corp. does not currently see many advantages that memory controller built-into central processing units (CPUs) would bring, as the firm has managed to increase performance without integration of memory controller with its forthcoming Core 2 processors. Nevertheless, in future the firm would integrate the appropriate circuits into its CPUs, moreover, it could add graphics capabilities to its chips, according to the company.
Speaking at a conference June 13, 2006, in New York hosted by analyst firm Bear Stearns Security, Dileep Bhandarkar, architect at large for Intel's digital enterprise group said that the company does not plan to integrate memory controller into its microprocessors set to be released in short-term, like Santa Clara, California-based chipmaker's arch-rival Advanced Micro Devices does.
Intel admitted that built-in memory controller helps to reduce memory access latencies and eliminate memory controller hub as an additional component. But the world's largest maker of microprocessors defended its current stance saying that by incorporating larger caches - on-chip memory pools - it can reduce memory latency impacts. At the same time, building memory controller into processor results in increased die size and power consumption of the CPU and reduces flexibility between supported memory types.
Speaking at a conference June 13, 2006, in New York hosted by analyst firm Bear Stearns Security, Dileep Bhandarkar, architect at large for Intel's digital enterprise group said that the company does not plan to integrate memory controller into its microprocessors set to be released in short-term, like Santa Clara, California-based chipmaker's arch-rival Advanced Micro Devices does.
Intel admitted that built-in memory controller helps to reduce memory access latencies and eliminate memory controller hub as an additional component. But the world's largest maker of microprocessors defended its current stance saying that by incorporating larger caches - on-chip memory pools - it can reduce memory latency impacts. At the same time, building memory controller into processor results in increased die size and power consumption of the CPU and reduces flexibility between supported memory types.