Wednesday, August 13th 2014

Intel Haswell TSX Erratum as Grave as AMD Barcelona TLB Erratum

Intel's "Haswell" micro-architecture introduced the transactional synchronization extensions (TSX) as part of its upgraded feature-set over its predecessor. The instructions are designed to speed up certain types of multithreaded software, and although it's too new for any major software vendor to implement, some of the more eager independent software developers began experimenting with them, only to discover that TSX is buggy and can cause critical software failures.

The buggy TSX implementation on Core "Haswell" processors was discovered by a developer outside Intel, who reported it to the company, which then labeled it as an erratum (a known design flaw). Intel is addressing the situation by releasing a micro-code update to motherboard manufacturers, who will then release it as a BIOS update to customers. The update disables TSX on affected products (Core and Xeon "Haswell" retail, and "Broadwell-Y" engineering samples).

TechReport's Scott Wasson draws a parallel between the TSX erratum, and the infamous translation lookaside buffer (TLB) erratum of AMD's "Barcelona" chips, which caused the company to temporarily halt production of its first single-die quad-core Opteron processors, and release similar "performance-impacting" micro-code updates for its consumer Phenom X4 processors. Expect your motherboard vendor to dish out a BIOS update with Intel's micro-code patch very soon.
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