Monday, November 8th 2021
AMD Could Use Infinity Cache Branding for Chiplet 3D Vertical Cache
AMD in its Computex 2021 presentation showed off its upcoming "Zen 3" CCD (CPU complex dies) featuring 64 MB of "3D vertical cache" memory on top of the 32 MB L3 cache. The die-on-die stacked contraption, AMD claims, provides an up to 15% gaming performance uplift, as well as significant improvements for enterprise applications that can benefit from the 96 MB of total last-level cache per chiplet. Ahead of the its debut later today in the company's rumored EPYC "Milan-X" enterprise processor reveal, we're learning that AMD could brand 3D Vertical Cache as "3D Infinity Cache."
This came to light when Greymon55, a reliable source with AMD and NVIDIA leaks, used the term "3D IFC," and affirmed it to be "3D Infinity Cache." AMD realized that its GPUs and CPUs have a lot of untapped performance potential with use of large on-die caches that can make up for much of the hardware's memory-management optimization. The RDNA2 family of gaming GPUs feature up to 128 MB of on-die Infinite Cache memory operating at bandwidths as high as 16 Tbps, allowing AMD to stick to narrower 256-bit wide GDDR6 memory interfaces even on its highest-end RX 6900 XT graphics cards. For CCDs, this could mean added cushioning for data transfers between the CPU cores and the centralized memory controllers located in the sIOD (server I/O die) or cIOD (client I/O die in case of Ryzen parts).
This came to light when Greymon55, a reliable source with AMD and NVIDIA leaks, used the term "3D IFC," and affirmed it to be "3D Infinity Cache." AMD realized that its GPUs and CPUs have a lot of untapped performance potential with use of large on-die caches that can make up for much of the hardware's memory-management optimization. The RDNA2 family of gaming GPUs feature up to 128 MB of on-die Infinite Cache memory operating at bandwidths as high as 16 Tbps, allowing AMD to stick to narrower 256-bit wide GDDR6 memory interfaces even on its highest-end RX 6900 XT graphics cards. For CCDs, this could mean added cushioning for data transfers between the CPU cores and the centralized memory controllers located in the sIOD (server I/O die) or cIOD (client I/O die in case of Ryzen parts).