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First AMD "Fiji" Package Shot

btarunr

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AMD CEO Lisa Su unveiled the company's next flagship graphics processor at an event on the sidelines of Computex, in Taipei. Arguably the biggest GPU package, measuring in at 50 mm x 50 mm, Fiji will instead reduce graphics card PCB size, because memory has been moved to the GPU package, with four 1024-bit HBM1 stacks surrounding the GPU die on the package. We detailed the chip's memory implementation at great lengths in this article. The first graphics cards based on this chip could be unveiled at E3, two weeks from now; and market launch could follow a week later.



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Hunky-dory, Fury must be a forceful girl.
 

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Hunky-dory, Fury must be a forceful girl.
And like most girls, takes an age to get ready for the dance.


So, 4GB confirmed (again) - kind of spoils the fun for the Chiphell jokesters.
 
Lisa Su has a bigger package then Jen-Hsun Huang
Yep, but remember hers is mostly old silicone*
Unless you meant that she has such a great record of success that she's now up to $11,748,072 for the salary package - positively dwarfs Jen-Hsun's $9.3m




* UMC's interposer is fabbed on the 65nm process
 
It will blow. many have not read the No-optimized clock. is not completed driver. That this new technology will have a beginner's problems can be speculate. a driver can be corrected.30% i assume .
 
It will blow. many have not read the No-optimized clock. is not completed driver. That this new technology will have a beginner's problems can be speculate. a driver can be corrected.30% i assume .

Wha?
 
thats one big chip.

Hopefully it gives GFX980TI a run for the money.
 
So, 4GB confirmed (again) - kind of spoils the fun for the Chiphell jokesters.
and what about if the 1024bit used in the sentence define the bus width .... and not capacity?

(don't hit me: i am just questioning ... )
 
and what about if the 1024bit used in the sentence define the bus width .... and not capacity?
Each HBM stack is 1024-bit which has been public since Hynix announced the tech. If you click the " Databook" link on the left hand side of the page you can access the product catalogue for shipping product ( SK Hynix ship the HBM to UMC who integrate the HBM stacks and GPU onto their interposer). You will see this:
gPOkW9y.jpg


1GB HBM DDR. The only difference between this and the specs that AMD seem to be using for the Fury is that AMD have programmed the DDR to run a little faster at 1.25Gbps (625MHz DDR) while upping the voltage to 1.3V VDDQ.
 
The bigger the chip, the bigger the fall...
 
Well that is something, so now we know what it looks like under the hood at least.
 
Considering that a third party game dev commented on the performance of this a month ago, and how tight lipped AMD is being by not putting a BIOS on the cards that might get out into the public hands they are busy with finishing touches now that the 980Ti is a known force and they want to make sure they don't fuck this up.
 
lisa! (who would the copilot of amd be?)
Judging by recent history, Lisa bails out ( golden parachute FTW), Devinder Kumar promoted to interim pilot takes over, and due to staffing cuts, Roy Taylor is promoted to co-pilot - as can be seen in this uncanny representation

tFPvOmz0uNmfp1sq2ebYAeUCLQ4-1024x576.jpg
 
*walks into her blowing (up) the doll, turns around embarrassed*
Unnecessary. The Roy Taylor automatically self inflates on contact with social media.
 
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