AMD Readies X370 High-end Chipset for "Summit Ridge" Processors

[BackSlash]

It's all about the Price - Performance. Can't wait!!
any clue about the target price of the new coming processor??

 

[TRWOV]

So there's going to be a sort of expansion "chipset" for m-ATX/ATX boards. Would ITX boards ship without this "chipset" or is it still a necessity?

 

[Bansaku]

People keep saying MB chipset....there is no MB chipset, right? It's all on die, no?

The Northbridge chipset is on die.

 

[TheGuruStud]

The Northbridge chipset is on die.

Which is the one that matters . SB is an afterthought, especially since it's only going to house, what, extra usb/sata and ethernet? It doesn't have much function anymore.

I remember when it used to handle legacy buses/interfaces. Get off my lawn!

It's just a plain IO controller, now. Chipset is giving it too much credit lol.

 

[$ReaPeR$]

so basically they are going the intel way with the huge difference of having only one socket. i like it!

 

[biffzinker]

Last I heard though I/O chipset (Southbridge) was integrated on die as well, same as Socket AM1. So is this the chipsets ASMedia was contracted to work on?

Edit:

Apparently, the source claims that "To save costs, AMD decided to cooperate with ASMedia in 2014 to license ASMedia's SATA Express patents and outsources its chip R&D and manufacturing to the chip designer."

http://news.softpedia.com/news/asme...amd-s-poor-financial-performance-486159.shtml

 

[FR@NK]

Looking at the older slides, it seems that each 4 core cluster does indeed have its own l3 cache.

Each core has its own 2MB L3 cache which can also be accessed by the other 3 cores in the CCU. Not sure if cores in another CCU has access.

so basically they are going the intel way with the huge difference of having only one socket. i like it!

One socket is a bad thing! It pretty much guarantees that even the high end chips will only have 20 PCIe lanes and only dual channel RAM.

 

[MisterEd]

No, its the architecture name, like Bulldozer or Piledriver.

Zen is AMD's latest microarchitecture. For example:
Family 15h Bulldozer
Family 16h Jaguar
Family 17h Zen
Note Piledriver is a 2nd generation Bulldozer.

 

[$ReaPeR$]

Each core has its own 2MB L3 cache which can also be accessed by the other 3 cores in the CCU. Not sure if cores in another CCU has access.



One socket is a bad thing! It pretty much guarantees that even the high-end chips will only have 20 PCIe lanes and only dual channel RAM.

not if they leave enough overhead for more powerful CPUs. the 2011 socket, for example, is used by CPUs with varying number of PCIe lanes.

 

[TheLaughingMan]

Each core has its own 2MB L3 cache which can also be accessed by the other 3 cores in the CCU. Not sure if cores in another CCU has access.

One socket is a bad thing! It pretty much guarantees that even the high end chips will only have 20 PCIe lanes and only dual channel RAM.

I am sure they have a way from each of the CCU's to "see" the data in the L3 cache. The question then because how and what is the overhead for moving data from one CCU to another. Will they need to clone the data over, parity, or will it just have direct read/write/copy access.

One socket is not a bad thing. A chip's PCI lanes can be modified in there design architecture. For example, there is no need for on-die graphics, large numbers of USB 3.1 connections, etc. on a server chip. So clearly the design would dictate everything you "drop" in comparison to an APU leaves more run to use those pins for high general purpose PCIe lanes, quad-channel memory, etc.

The also never confirmed the chip size would not change. Even if the socket is the same 1331 pin out to the chip, a server class chip could be larger or wider, just with the same 1331 pins in the same grid in the middle.

 

[FR@NK]

there is no need for on-die graphics, large numbers of USB 3.1 connections, etc. on a server chip. So clearly the design would dictate everything you "drop" in comparison to an APU leaves more run to use those pins for high general purpose PCIe lanes, quad-channel memory, etc.

The pins on the socket cant change from USB to quad channel memory or anything else because then the socket would lose compatibility between different chips. The motherboard cant re-wire itself just because you install a CPU that doesnt have an integrated GPU. Hopefully farther down the road they release a higher end socket for the enthusiast market.

 

[TheLaughingMan]

The pins on the socket cant change from USB to quad channel memory or anything else because then the socket would lose compatibility between different chips. The motherboard cant re-wire itself just because you install a CPU that doesnt have an integrated GPU. Hopefully farther down the road they release a higher end socket for the enthusiast market.

Kinda my point. AMD promised to use the same socket across the board. They never promised cross compatibility. There is no reason AMD has to not have server parts and motherboards with the same socket be wired completely differently during the engineering/design phase. I don't see the server segment working on consumer boards even if they have the same pin count and socket. What would be the point of allow consumer desktops the option of installing some 16+ core 2.0 GHz chip in an X370 consumer board?

 

[FR@NK]

AMD promised to use the same socket across the board

You only get 8 cores max on the AM4 socket.

The server chips will have to have its own socket since AMD is saying they will have 8 DDR4 channels which wont fit within 1331 pins. I just hope they release enthusiast desktop chips on the server socket or else AMD wont be able to compete at the high end.