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AMD to Cough Up $12.1 Million to Settle "Bulldozer" Core Count Class-Action Lawsuit

When people don't understand, they are going are to see what they want to see regardless if the proof is right there in front of them.

Indeed, at the end of the day that's the biggest issue here.

Big square blocks that are arranged symmetrically, preferably with a bright red border, that's the only definition that they'll accept for a core because that's the extent to which their understanding goes.
 
Well, seronx is of course completely correct in what constitutes a core.
The problem with applying this to Bulldozer is that the resulting core is not exactly useful to us. AMD64 RISC is not exposed in any way. X86 goes out the window the moment you remove frontend.
 
Low quality post by Chrispy_
Bulldozer was the perfect example of sunk-cost fallacy.

$12.1M is small change that AMD will gladly give to put dubious advertising behind them. If only such a lawsuit were applied to Donald Trump or Brexit....
 
X86 goes out the window the moment you remove frontend.
The benefit is that it is defined as an accelerator. Just like upgrading a GPU(part of the system, but not part of the CPU) they can improve the front-end. Modified without modifying the cores.

The front-end for a monolithic dual-core can be statically partitioned between cores in multi-core fashion(CMP2).
The front-end for a monolithic dual-core can be competitively shared between cores in vertical multithreaded fashion(VMT2).
The front-end for a monolithic dual-core can be algorithmic-priority partitioned between cores in simultaneous multithreaded fashion(SMT2).
The front-end for a monolithic dual-core can be competitively partitioned between cores in clustered multithreaded fashion(CMT2).

Even in VMT just because it fetches/decodes/dispatches for a single core, doesn't mean there aren't two cores. As the FE isn't actually a defining feature of a core, it's an optional feature. They could always skip the front-end and directly interconnect to the cores themselves.

---
Including the FPU, one would have to prove against a similar design that they made a FPU that is only optimized for single-core usage.

Husky per core; 1x 128-bit add + 1x128-bit mul + 1x128-bit fmisc // 84-entry flight window + 42-entry FPU scheduler + 120-entry PRF <== 32-nm node
Bobcat per core; 1x 64-bit add + 1x 64-bit mul // 40-entry flight window + 18-entry FPU scheduler + 88-entry PRF <== 40-nm node
Bulldozer per dual-core; 2x 128-bit Fused-multiply add, 2x 128-bit Packed Integer vALUs // 2*128-entry flight window + 64-entry FPU scheduler + 160-entry PRF <== 32-nm node
Zen per core; 2x128-bit FMUL, 2x128-bit FADD // 192-entry flight window + 36-entry FPU scheduler + 160-entry PRF <== 14-nm node

Clearly, that is not the case.

40nm => 160nm CPP/120nm Mx, 130nm My, and within Intel's 32nm league with density, thus within spitting of GloFo's 32nm.
32nm => 130nm CPP/104nm Mx, two cores Husky and Bulldozer.
14nm => 78nm CPP/64nm Mx, basically two full nodes from 32nm.
 
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Is ALU enough to be a core?
It needs a control unit, instruction bus, data bus as well.
Have a look here:
AMD_Bulldozer_block_diagram_%288_core_CPU%29.PNG

"control unit" = "Core IF"
There's only four of those, because there's only four cores.

View attachment 130309View attachment 130310

When people don't understand, they are going are to see what they want to see regardless if the proof is right there in front of them. Also if you slice the second image horizontally across and swap the bottom and top then rotate the image 90 degrees it looks an awfully a lot like the first.
Except your lines are completely wrong on Bulldozer (but right on the 8-core Xeon). You just evidenced that they aren't cores because, as Feng said, "core replication is obvious."
amd_bulldozer_core_module_zoom.jpg

...I'm not even sure that picture is 100% accurate...


AMD settled.
In civil lawsuits, settlement is an alternative to pursuing litigation through trial. Typically, it occurs when the defendant agrees to some or all of the plaintiff's claims and decides not to fight the matter in court.
Integer clusters are not cores and the plaintiffs were, in fact, mislead by AMD's claims to the contrary. If AMD tries to create a CMT architecture in the future, this case will be used as precedent to again declare that integer clusters are not cores.
 
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Idk, Piledriver is pretty good today vs when it first appeared.

Ohwell, what I have still does what it does. Fx 8350.
 
"control unit" = "Core IF"
There's only four of those, because there's only four cores.
The control unit is within this image;
retirequeue.png


On a native octo-core, there eight of them on the die. On AMD's Husky this unit is called the Instruction Control Unit. Even though it is renamed in this image it still is the control unit.
 
That doesn't look like Bulldozer, how is it relevant?
 
AMD settled.

Integer clusters are not cores and the plaintiffs were, in fact, mislead by AMD's claims to the contrary. If AMD tries to create a CMT architecture in the future, this case will be used as precedent to again declare that integer clusters are not cores.
ok they "settled" ... just to get rid of this ... but that doesn't make the thing right ...

i.e.: a friend has an argument i don't agree and is very stubborn with it, (in that case, that was also about core count on something but i can't remember what it was :p ah yes ... it was on core count of a Pentium 4 HT back in the days ) i tell him "ok ok, you are right, in your own perception, ok i pay you a beer so we can settle this" so he can stop rambling about it and trying to prove his point.

4 dual core module which each core on each modules share the same FPU/Scheduler is, 4x2=8, an octacore (if it was a quadcore ... it wouldn't beat a Intel Equivalent quadcore on certain heavily threaded application and not only by a 2more core margin same for the hexacore FX 6XXX which had 3 dual core modules .)

they paid so it can shut up.


other than that, you are right, wanna grab a beer? :toast:
 
It was. GTX970 had 4GB of DDR5.
It wasn't DDR5 all of it as it was written in the specs...:p
The performance was so poor that it didn't even come close to qualifying as DDR5. So, simpleminded appraisals of the situation fail.

By contrast, despite the weakness of the individual cores in Bulldozer/Piledriver, 8 of its cores were faster than 6 or 4 or 2 or 1.

Apples and oranges comparison. The 512 MB partition of the 970 was completely unacceptable in its extreme slowness. It was a clear case of fraudulent marketing.

"Half-truths" are not truths. When the performance is as bad as it was for that partition it doesn't qualify in anyone's book for DDR5-class.
 
That is a Bulldozer core. Of which, there are two in a module.
The layout is completely wrong. On that note, I found a document where AMD themselves laid out the core structure:
BulldozerHotChips.png


There's also a contradiction in this document in the intro:
It combines two independent cores intended to deliver high per-thread throughput with improved area and power efficiency. A monolithic building block, the Bulldozer module can execute two threads via a combination of shared and dedicated resources.
Those are antonyms.
 
ok they "settled" ... just to get rid of this ... but that doesn't make the thing right …
You don't settle if you the facts are on your side.
 
You don't settle if you the facts are on your side.
it's not about fact but about perception as i mentioned in the example i used ... an INT/LS (EX/LS) is a core ... but some don't view it as one ... so it isn't a core?

as i said ... wanna grab a beer? you are right.

additionally ... not everythings ruled by a court is 100% right ...
 
You don't settle if you the facts are on your side.
The fact is that the court system isn't about objective truth. It's about optics.

(This, incidentally, also works in the favor of corporate executives. Insiders on MSNBC, for example, stated — without a hint of concern over the morality of the policy — that the Justice Department has a strong "unofficial" policy of going out of its way to not charge corporate executives with crimes — instead resorting to fines. The argument the insiders presented, which is utterly specious, is that the policy is better for the little people — the workers at the corporations — because, according to the broken logic, fines won't put companies out of business but, somehow, sending executive-class criminals to jail will. This illogic requires the absurd belief that those jobs can't be filled by others. It also ignores the apparent fact that those fines are more likely to come out of the compensation package/jobs of the lower-level workers than they are likely to dent the golden parachutes of the CEOs and such.)
 
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Courts aren't involved in settlements.
same kind same kind ... settlements is the end of the path and well ... whatever ... sooooo, about that beer ...?
 
Courts aren't involved in settlements other than filings. Settlements are private contracts.
The article I linked to said a judge has to approve the settlement.

"Fine and forget" is the standard operating procedure for the transfer of wealth into the upper crust these days. It gives the system the illusion of accountability.
 
same kind same kind ... settlements is the end of the path and well ... whatever ... sooooo about that beer ...?
I don't do alcohol. :rolleyes:


There's something about Bulldozer that's unique to its first iteration of design that was never done before it:
BulldozerCacheHierarchy.png

Instruction decode is 1:2 instead of 1:1. This proves dependence because without an independent means to decode instructions, the integer clusters cannot operate independently.

AMD proved this was a design flaw because in Steamroller, they decided to not share instruction decode...
AMD_Steamroller_CPU_Design-640x354.jpg

...they wouldn't have done that if their original argument was correct. They decided more independency is better, affirming the plaintiffs argument that AMD misrepresented their product.
 
The best thing AMD could have done was to settle for this trifle of money (12.1 million dollars). Even if they believed they had a good defense and were lawyered up to the teeth. Most lawyers will tell you that when it comes to a jury they are unpredictable. AMD might have won the case at trial but they may have lost in a much bigger way. You never know with a jury. I think in a civil case only 9 out of the 12 jurors have to agree on a verdict. They might have found for the plaintiff and awarded full compensation for the cost of the Bulldozer CPUs to the plaintiffs. Now were up to around 80 to 100 million dollars. Additionally, I think, they might have even awarded punitive damages.
 
AMD proved this was a design flaw because in Steamroller, they decided to not share instruction decode...

...they wouldn't have done that if their original argument was correct.
Steamroller did not replace Piledriver. It was originally supposed to be designed for the high-performance bracket but AMD changed course and made Steamroller a weaker product to fit into the niche of reduced power consumption and production cost. That is why it never came in 8 cores and it was made on the inferior 28nm node.

Jaguar also had design compromises to fill its reduced power consumption and reduced production cost niche. It is hardly a repudiation of Bulldozer/Piledriver either as it has worse IPC than even Bulldozer as far as I know.

Piledriver was the direct replacement for Bulldozer and it was never replaced until Zen 1.
 
AMD proved this was a design flaw because in Steamroller, they decided to not share instruction decode...
...they wouldn't have done that if their original argument was correct. They decided more independency is better, affirming the plaintiffs argument that AMD misrepresented their product.
Um, that(those) instruction decode(s) isn't part of the core.
 
I don't do alcohol. :rolleyes:


There's something about Bulldozer that's unique to its first iteration of design that was never done before it:
View attachment 130329
Instruction decode is 1:2 instead of 1:1. This proves dependence because without an independent means to decode instructions, the integer clusters cannot operate independently.

AMD proved this was a design flaw because in Steamroller, they decided to not share instruction decode...
AMD_Steamroller_CPU_Design-640x354.jpg

...they wouldn't have done that if their original argument was correct. There had to be a reason why they decided more independency is better, affirming the plaintiffs argument that AMD misrepresented their product.
are all beer alcoholic? pffff ... not fun ... (plus it's one of the most wholesome drink in the whole world ... drink responsibly and alcohol is not an issue ... ) "point of view"

still 8 core on 4x2core module.

not a fact, a point of view on what is a INT/LS (EX/LS) (hint: a core...)

steamroller has the same INT/LS (EX/LS) pair of core per module ... they just splitted the decode in 2 soooooo "2 INT/LS (EX/LS) 1 decode" is a single core and "2 INT/LS (EX/LS) 2 decode" is a dual core .... sooooo the core are defined by the decode unit? (hint they are not, that class action lawsuit was only a mean to cash on the fact that BD was slower than intel ... although on certain heavily threaded applications ... they weren't but those who use that wouldn't fill a class action lawsuit ... because it only really mattered in gaming performance ... thus: pissing in the wind)

soooo how about that non alcoholic beverage of your choice?
 
If I remembered correctly, IBM PowerPC also use same methods in earlier day of their multi threads implementation.
One question remains, how these court filling applied to, will it's applied to all Bulldozer uArch and derivatives?
 
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