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Samsung Electronics is reportedly developing its 7th generation V-NAND memory with ultra-high 3D stacking technology. The first model will feature at least 160 layers, subsequent models will feature more. In early signs of the company not wanting to yield the technological initiative to China's YMTC, the first 160-layer V-NAND by Samsung is slated to come out roughly around the time YMTC's 128-layer 3D NAND flash hits mass production, towards the end of 2020.
At the heart of the ultra-high 3D stack is Samsung's proprietary Double Stack technology. The double-stack technology creates electron holes at two separate times for current to go through circuits. The current-generation single-stack chips creates these holes once throughout the stack per cycle. The 160-layer NAND flash is expected to herald a 67% increase in densities per package over the 96-layer chips in the market. Densities could also be increased by other means such as switching to newer semiconductor fabrication nodes, and PLC (5 bits per cell), which is currently being developed by KIOXIA.
View at TechPowerUp Main Site
At the heart of the ultra-high 3D stack is Samsung's proprietary Double Stack technology. The double-stack technology creates electron holes at two separate times for current to go through circuits. The current-generation single-stack chips creates these holes once throughout the stack per cycle. The 160-layer NAND flash is expected to herald a 67% increase in densities per package over the 96-layer chips in the market. Densities could also be increased by other means such as switching to newer semiconductor fabrication nodes, and PLC (5 bits per cell), which is currently being developed by KIOXIA.
View at TechPowerUp Main Site
