Samsung Develops 512 GB DDR5 Memory Modules Running at 7.2 Gbps

[TokyoQuaSaR]

It is simple, basic Maths. Just divide by 2, or by 4, or by 8 depending on the memory standard.

Basically divide only by 2, there is only DDR memory in the market, we don't see QDR except in rare embedded applications and I don't think that there is any memory standard with 8 data per cycle per pin.

 

[Wirko]

Basically divide only by 2, there is only DDR memory in the market, we don't see QDR except in rare embedded applications and I don't think that there is any memory standard with 8 data per cycle per pin.

If I understand the available data correctly, it should be 4 for GDDR6X. There are two data transfers per clock period, and two bits per transfer, as PAM4 is employed.

GDDR6, on the other hand, can operate either at double or quad data rate (the latter requires halving the clock frequency, WCK). Check out this document from Micron, page 11.

Anyone (old enough) want to calculate the baud rates?

 

[TokyoQuaSaR]

If I understand the available data correctly, it should be 4 for GDDR6X. There are two data transfers per clock period, and two bits per transfer, as PAM4 is employed.

GDDR6, on the other hand, can operate either at double or quad data rate (the latter requires halving the clock frequency, WCK). Check out this document from Micron, page 11.

Anyone (old enough) want to calculate the baud rates?

I guess you're right, totally forgot about the GDDR5-6X with PAM4 indeed. But well it's not like we can choose it separately anyway.
Baud rate in this case should be half the bit rate (10GBaud for GDDR6X 20Gb/s).