For AM4 user it's still a new socket
AM4 has at least three microarchitecture changes, not just refinement.
Zen 1.0 has quad 128-bit SIMD units.
Zen 1.5 has 12 nm refinements from 14 nm.
Zen 2.0 has quad 256-bit SIMD units.
Zen 3.0 has quad 256-bit SIMD and two extra FPU units expansion. Load-Store unit count expansion. Some AVX-512 instruction support e.g. AVX-512 Vector AES, AVX-512 Carry-Less Multiplication Quadword.
Zen 3 X3D cache. L3 cache expansion.
Reminds me that Athlon XPs don't have SSE2, but they have the first SSE, like Pentium III. Athlons before Palomino, didn't even have SSE at all.
And before that, K6-2 didn't have an instruction that Pentium IIs had!
Uggh, looks like history repeating itself again!
K6-2 has 64-bit 3DNow SIMD (64-bit hardware implementation) which includes Pentium II's MMX SIMD. K6-2 doesn't support Pentium III's SSE (64-bit hardware implementation).
Pentium III's 128-bit SSE is implemented on 64-bit SSE hardware until Core 2's full 128-bit bit SSE hardware.
K8 has 128-bit SSE FADD and 64-bit FMUL SIMD hardware. Pentium IV has 64-bit SSE hardware implementation.
K10 has 128-bit SSE FADD and 128-bit FMUL SIMD hardware with K8's three instructions per cycle decoder limitations. Core 2's full 128-bit bit SSE hardware has four instructions per cycle decoders.
The instruction set may not follow actual hardware implementation.
PowerPC's Altivec 128-bit SIMD competition has 128-bit hardware implementation at PowerPC G4's introduction i.e. no bulldust 64-bit SIMD hardware with fake 128-bit SIMD instruction set.