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AMD EPYC 8004 "Siena" Processors with "Zen 4c" and New SP6 Platform Announced

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AMD today rolled out the new compacted Socket SP6 server platform designed for smaller servers locally deployed at the edge by organizations. With CPU core-counts of up to 64-core/128-thread, these processors are based on the "Zen 4c" microarchitecture, which comes with identical IPC and ISA to "Zen 4," but with smaller L3 cache available per core. The EPYC 8004 series targets traditional data-centers located on-site for organizations. Even if the heavy-lifting of the IT for them is performed by remote data-centers or cloud providers, organizations still need smaller edge server deployments. The EPYC 8004 series caters to a different kind of servers than the ones the lower core-count models of EPYC 9004 "Genoa" do.

With the EPYC 8004 series, AMD is debuting a new smaller CPU socket called SP6. The socket measures 58.5 mm x 75.4 mm, compared to the 76.0 mm x 80.0 mm of Socket SP5 powering EPYC 9004 "Genoa" and EPYC 97x4 "Bergamo." Socket SP5 is an LGA with a pin count of 4,844, compared to SP5, which is LGA-6096. The first line of processors for this socket, the EPYC 8004 series, are codenamed "Siena." These are very much part of the 4th Gen EPYC series, a lineage it shares with "Genoa" for data-center servers, "Genoa-X" for compute servers, and "Bergamo" for high-density cloud.



EPYC 8004 "Siena" is a chiplet-based processor, much like "Genoa." It uses the same 6 nm server I/O die (sIOD), but with nearly half its I/O capabilities cut down. This sIOD is surrounded by four 5 nm CCDs codenamed "Vindhya." Each of these has 16 CPU cores based on the "Zen 4c" microarchitecture, spread across two CCX (CPU core complex). Each CCX has eight "Zen 4c" cores sharing a 16 MB L3 cache. Each of these cores has 1 MB of dedicated L2 cache. "Vindhya" is the same CCD found in the EPYC "Bergamo" processor AMD designed for Socket SP5.



As we detailed in several articles related to "Bergamo" and "Phoenix 2," the new "Zen 4c" CPU core is a physically compacted version of the "Zen 4" core, it has no missing hardware features. Both CPU core types have an identical IPC, as well as the same instruction sets, so any software designed specifically for EPYC "Genoa" should run seamlessly on "Siena." The "Zen 4c" core is 35% smaller in area than "Zen 4," and so AMD has been able to build a CCD with 16 of these cores, albeit with smaller L3 caches.

AMD EPYC 8004 processors come with a leaner I/O than their Socket SP5 cousins. The processor only has a 6-channel DDR5 memory interface, which can drive up to 1,152 GB of ECC DDR5-4800 RDIMM memory. The PCI-Express root complex has been slimmed, too. "Siena" puts out a total of 96 PCI-Express Gen 5 lanes, and 48 CXL 1.1 lanes. The sIOD-based AMD Infinity Guard security architecture gets carried over from the other 4th Gen EPYC processors untouched.


With a CPU core count of up to 64, AMD has carved out six processor SKUs, along with variants that meet NEBS certification. The EPYC 8024P is an 8-core/16-thread processor with 2.40 GHz base and 3.00 GHz boost frequencies; a default TDP of 90 W, and a starting price of $409. Its NEBS-friendly variant, the 8024PN ticks at 2.05 GHz base frequency, with 80 W TDP, and has a wider temperature operating range. This one is priced at $525. The 16-core/32-thread EPYC 8124P ticks at 2.45 GHz base, 3.00 GHz boost, and has a 125 W TDP, and a $639 price tag. Its sibling, the 8124PN runs at 2.00 GHz base, with a 100 W TDP, and a steeper $790 price.

A step up from these two are the 24-core/48-thread EPYC 8224P (2.55 GHz/3.00 GHz, 160 W TDP, $855 MSRP); and the 8224PN (2.00 GHz base, 120 W TDP, $1,105 MSRP); and the 32-core/64-thread 8324P (2.65 GHz/3.00 GHz, 180 W TDP, $1,895 MSRP); and the 8324PN (2.05 GHz base, 130 W TDP, and $2,125 price). At the top of the stack are the 48-core/96-thread EPYC 8434P (2.50 GHz base/3.00 GHz boost, 200 W TDP, $2,700 MSRP), followed by the 8434PN at lower 2.00 GHz base, and 155 W TDP, for $3,150. Leading the pack is the 64-core/128-thread EPYC 8534P running at 2.30 GHz base, 3.10 GHz boost, with 200 W TDP, and a $4,950 price-tag. It NEBS-friendly variant, the 8534PN, ticks at 2.00 GHz base, 3.00 GHz boost, and has lower 175 W TDP, but a steeper $5,450 price.


The EPYC 8004 "Siena" has a generally lower TDP compared to "Zen 4" based EPYC 9004 "Genoa" processors of comparable core-counts, which range between 200 W to 400 W. This is because of lower frequencies across the board, more CPU cores per CCD, fewer CCDs, smaller caches, and the sIOD running with reduced I/O capabilities.

In terms of performance, AMD is claiming an up to double performance per 1P system-Watt compared to the 4th Gen Intel Xeon Platinum 8490H (60-core/120-thread), and Platinum 8471N (52-core/104-thread). The company is also claiming that at identical core-counts, with the 32-core/64-thread EPYC 8324P pitted against the Xeon 6421N, you get around 16% higher video transcoding performance per core (FFmpeg). These processors over 40% higher performance per system-power; and 32% lower estimated system power; along with 80% higher core density per rack, and 40% higher throughput per rack.



AMD is releasing the EPYC 8004 series through leading server vendors, as well as in trays to server integrators. The company has a vast ecosystem of companies designing server motherboards, fully built server blades and racks, built around these processors.


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Bergamo CPUs have 112 or 128 cores, they are only for applications that require great many cores. For everything else, there's Genoa.

However, AMD took a different path here and also launched CPUs with very few cores. I'm wondering what's the purpose ... some storage servers possibly, which require little processing power but a lot of PCIe? 96 lanes can be split into x2 links and connect to 48 SSDs without additional switches, not at Gen5 speeds because running cables is basically imposible but Gen3 at the minimum should be possible.
 
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Bergamo CPUs have 112 or 128 cores, they are only for applications that require great many cores. For everything else, there's Genoa.

However, AMD took a different path here and also launched CPUs with very few cores. I'm wondering what's the purpose ... some storage servers possibly, which require little processing power but a lot of PCIe? 96 lanes can be split into x2 links and connect to 48 SSDs without additional switches, not at Gen5 speeds because running cables is basically imposible but Gen3 at the minimum should be possible.
Siena was always advertised for telco.
 
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Siena was always advertised for telco.
"Edge", they now say. That's a broad term.

I'm not familiar with what telcos need and use. Maybe they need to connect a large number of wireless transmitters and receivers, plus wires and optics, to all those PCIe lanes.
 
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"Edge", they now say. That's a broad term.

I'm not familiar with what telcos need and use. Maybe they need to connect a large number of wireless transmitters and receivers, plus wires and optics, to all those PCIe lanes.
There is a little more info in some of the other press releases like this one:


But yeah Edge has been added to the list of targeted markets and it is broad indeed.
 
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It already happened. Its called Bergamo.
Sorry I thought Bergamo was the tech and Sienna was the implementation. So different product stacks. Why not just make Bergamo in 128 and 64 core versions. There must be a lot of differences between Sienna and Bergamo to warrant a new product class.
 
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