Intel Announces Intel 14A (1.4 nm) and Intel 3T Foundry Nodes, Launches World's First Systems Foundry Designed for the AI Era

[Eternit]

It's not incorrect, 14 angstrom translates to 1.4 nm. It is a simple divide nanometer by 10 formula. However, it remains that it's a marketing term, transistor and fin pitch sizes are obviously nowhere near close to the 10 nm realm, let alone 7, 5 or 3. The use of nanometers in lithography has been inaccurate for a very long time, it's simply a marketing quirk nowadays.

Yes 14 Angstrom is 1.4nm, but Angstrom symbol is Å not A. 14A is not 14Å like Intel 4 is not 4nm like TSMC N5 is not 5nm. They are just marketing names.

i get the feeling that 14A would be the new 14NM that lasted for a decade 5-11th gen provided they can even manage to get it off the ground.

I don't know where youtr feeling comes from? Just because number 14 is in both 14nm and 14A?
Anyway 14nm wasn't great in the beggining, maybe not as bad as 10nm in the begining, but still far from being great.
Intel started production on 22n in 2012 but took them another 2 years before they were producing high quality chips. Ivy Bridge and Haswell refresh.
They started 14nm in 2014, but took them 3 years before they were producing high quality. Broadwel 2014 l and Coffee Lake 2017
The same with 10nm/Intel 7. 2018 Cannon Lake and 2022 Raptor Lake.
They were able to squeeze even more with Rocket Lake and Raptor Lake refresh.
So probably it will be the same with 7nm/Intel 4-3 in a few years they will yield great CPUs. And the same with 5nm Intel 20A 18A and later with 14A (3nm?).

 

[3valatzy]

You probably know this already but when they talk about such numbers, they clarify what kind of process it is. If they achieve 85% of theoretical that's damn good. Oftentimes it falls far short, not surprising to be under 50% of the number. So it'd be 0.5 x HP process and 0.5 x HD process.

Apple's first TSMC 3 nm A17 Bionic: 100 mm2 19B transistors - that's 190 MTr / mm2 or ~85%.
AMD's GCD in Navi 31: 304.35 mm2 45.4B transistors - that's 150.2 MTr / mm2 or 176.7 Mtr / mm2 for the TSMC 5 nm.

Wikipedia states something very weird:
TSMC 5 nm = 138.2 MTr / mm2
TSMC 3 nm = 224.2 Mtr / mm2

 

[DavidC1]

Apple's first TSMC 3 nm A17 Bionic: 100 mm2 19B transistors - that's 190 MTr / mm2 or ~85%.
AMD's GCD in Navi 31: 304.35 mm2 45.4B transistors - that's 150.2 MTr / mm2 or 176.7 Mtr / mm2 for the TSMC 5 nm.

Wikipedia states something very weird:
TSMC 5 nm = 138.2 MTr / mm2
TSMC 3 nm = 224.2 Mtr / mm2

They probably got something wrong with Navi 31 numbers. Otherwise based on the performance what are those transistors doing?

 

[3valatzy]

They probably got something wrong with Navi 31 numbers. Otherwise based on the performance what are those transistors doing?

If memory serves me well, an article claimed that AMD doesn't want to enable all the potential and features of Navi 31 because Nvidia didn't compete.

 

[N/A]

Because that's the GCD density. the MCD is far less 1/3 basically and it can't be shrinked that much more. so you get 109 average. Nvidia gets 122

I don't know where youtr feeling comes from? Just because number 14 is in both 14nm and 14A?
Anyway 14nm wasn't great in the beggining, maybe not as bad as 10nm in the begining, but still far from being great.

2014 Q4 14nm lasted for 5,6,7,8,9,10,11 gens 2021 10nm formerly known still dragging itself well into the 3rd year 12,13,14th gen
now 2024 is supposed to be the year when 20A (3NM old) is released in mass volume for the CPU tile
How is that even possible they skipped the old 7 and 4. will be used for other tiles but still.

 

[AMDK11]

From what I've researched, the 13900k (intel 7) has 25.9B transistors, so if the die is 258mm², that's 100mT/mm².

Intel's process density isn't bad, the same goes for Samsung; the problem is that in terms of efficiency, both are crawling at the feet of TSMC

Where does the data on the number of transistors for the RaptorLake-S system come from?

 

[3valatzy]

Because that's the GCD density. the MCD is far less 1/3 basically and it can't be shrinked that much more.

If this is true, then AMD made a mistake to make the MCD using the still expensive N6 process. They could have used something much cheaper - for example 45 nm or 32 nm... whatever suits them to lower the cost and the SEP.

 

[AMDK11]

Zen 2
7nm TSMC Compute die
~76 mm2
3.8B xtors
50 MTr/mm2

Zen 3
7nm TSMC Compute die
~84 mm2
4.15B xtors
49.40 MTr/mm2

Zen 4
5nm TSMC Compute die
~71 mm2
6.57B xtors
92.54 MTr/mm2

 

[Eternit]

Because that's the GCD density. the MCD is far less 1/3 basically and it can't be shrinked that much more. so you get 109 average. Nvidia gets 122


2014 Q4 14nm lasted for 5,6,7,8,9,10,11 gens 2021 10nm formerly known still dragging itself well into the 3rd year 12,13,14th gen
now 2024 is supposed to be the year when 20A (3NM old) is released in mass volume for the CPU tile
How is that even possible they skipped the old 7 and 4. will be used for other tiles but still.

The first Intel 10nm CPU was in 2018, it was a disaster but anyway it was in 2018 so it is dragging into 6th year.
Also Intel 3 is just improved Intel 4 and they both are what used to be named 7nm. 20A and 18A will be what used to be 5nm and 14A what used to be 3nm. All these names are just marketing.

 

[Denver]

If this is true, then AMD made a mistake to make the MCD using the still expensive N6 process. They could have used something much cheaper - for example 45 nm or 32 nm... whatever suits them to lower the cost and the SEP.

Implementing such 'brilliant' ideas would likely lead AMD to produce a stove rather than a GPU.

The GTX 580 (40nm) was 520mm2 @ 3B transistors. As the cache is always less dense, expect something like twice the size, 1040mm. Therefore, a silicon notebook, rather than a GPU. Useless... Moreover, the inter-die connection technology required would likely be impractical or non-functional.

The MCM design makes the chip a little more inefficient. However, the N31's problem is more about software than hardware. Nvidia extends its tentacles, putting engineers working in every possible studio, even indies, to make everything run better on its hardware. AMD dealing with Intel and Nvidia at the same time cannot do this to the same degree.

Where does the data on the number of transistors for the RaptorLake-S system come from?

I don't remember if it was an estimate from the chiphell or semi-accurate forums, maybe it's close to reality or not

 

[3valatzy]

Implementing such 'brilliant' ideas would likely lead AMD to produce a stove rather than a GPU.

A 14 nm SRAM cell is 0.0588 µm2, N6's SRAM cell size is 0.027 μm2. Difference is 117%.
Navi 31's MCD is 225.12 mm2, that made on a 14 nm process would be equivalent to 489 mm2.
If AMD was smart, decrease the Infinity cache size and make the MCD using the older process.

Wafer prices - < 3000$ for 14 nm
Wafer prices - between 9000 and 10000$ for 6 nm.

It is a brilliant idea.

Actually, TBH, if AMD had those "brilliant minds", it wouldn't be in that situation it is in now.

 

[Denver]

A 14 nm SRAM cell is 0.0588 µm2, N6's SRAM cell size is 0.027 μm2. Difference is 117%.
Navi 31's MCD is 225.12 mm2, that made on a 14 nm process would be equivalent to 489 mm2.
If AMD was smart, decrease the Infinity cache size and make the MCD using the older process.

Wafer prices - < 3000$ for 14 nm
Wafer prices - between 9000 and 10000$ for 6 nm.

It is a brilliant idea.

Actually, TBH, if AMD had those "brilliant minds", it wouldn't be in that situation it is in now.

MCD at 6nm costs just US$7-8; This chip is so small that a single wafer easily yields more than 1200 chips. Designing with such an outdated process not only introduces inefficiencies but also escalates costs, rendering it incompatible with AMD's current and future technological strategies, which prioritize the development of increasingly modular products.

Then... Yes, following your ideas is useless.

 

[AnotherReader]

If this is true, then AMD made a mistake to make the MCD using the still expensive N6 process. They could have used something much cheaper - for example 45 nm or 32 nm... whatever suits them to lower the cost and the SEP.

N6 is a variant of N7 which was the last node with good SRAM scaling so it would have been a mistake to make the MCDs on an older node.

The first Intel 10nm CPU was in 2018, it was a disaster but anyway it was in 2018 so it is dragging into 6th year.
Also Intel 3 is just improved Intel 4 and they both are what used to be named 7nm. 20A and 18A will be what used to be 5nm and 14A what used to be 3nm. All these names are just marketing.

Intel 3 and 4 are closer to TSMC's N5 than their N3. Don't go by marketing names. Look at actual feature sizes.

 

[3valatzy]

MCD at 6nm costs just US$7-8; This chip is so small that a single wafer easily yields more than 1200 chips. Designing with such an outdated process not only introduces inefficiencies but also escalates costs, rendering it incompatible with AMD's current and future technological strategies, which prioritize the development of increasingly modular products.

It doesn't work like that.
You state the cost of 1 MCD. They put 6 of them - that's at least 42$.

Also, unite those cut 6 MCD into a single die on a 14 nm.

There is a reason why the RAM manufacturers use 1x nodes, not 7 nm.

 

[AnotherReader]

It doesn't work like that.
You state the cost of 1 MCD. They put 6 of them - that's at least 42$.

Also, unite those cut 6 MCD into a single die on a 14 nm.

There is a reason why the RAM manufacturers use 1x nodes, not 7 nm.

The processes used for DRAM are very different from logic processes. There's a reason that TSMC doesn't manufacture DRAM and Intel stopped manufacturing DRAM. Uniting the 6 MCD would also limit the utility of the new MCD. With the current approach, just scaling the number of MCDs allows AMD to offer the 7700 XT, 7800 XT, 7900 XT and 7900 XTX.

 

[Denver]

It doesn't work like that.
You state the cost of 1 MCD. They put 6 of them - that's at least 42$.

Also, unite those cut 6 MCD into a single die on a 14 nm.

There is a reason why the RAM manufacturers use 1x nodes, not 7 nm.

Yes, It's because they are different technologies, I see that you have no idea what you are talking about...

SRAM; Uses flip-flops to store each bit of data. A flip-flop consists of several logic gates that maintain their state (0 or 1) as long as power is maintained.

DDR RAM: Uses storage cells based on capacitors and transistors to store bits. Each cell contains a capacitor that stores electrical charge to represent a bit.

 

[AMDK11]

Intel 7(E10SF)

"Some news for Sapphire Rapids from ISSCC: According to Nevine Nassif, Principal Engineer for Sapphire Rapids at Intel, the die size is a little lower than 400 mm² and the transistor count is between 11 and 12 billion."

https://twitter.com/i/web/status/1495821855667671041

Intel 7(E10SF)
"Some news for Sapphire Rapids from ISSCC: According to Nevine Nassif, Principal Engineer for Sapphire Rapids at Intel, the die size is a little lower than 400 mm² and the transistor count is between 11 and 12 billion."

Where did the 26 billion transistors in RaptorLake-S come from?

Intel 7 is definitely not 100 MTr/mm2.

 

[Denver]

Intel 7(E10SF)

"Some news for Sapphire Rapids from ISSCC: According to Nevine Nassif, Principal Engineer for Sapphire Rapids at Intel, the die size is a little lower than 400 mm² and the transistor count is between 11 and 12 billion."

https://twitter.com/i/web/status/1495821855667671041

Intel 7(E10SF)
"Some news for Sapphire Rapids from ISSCC: According to Nevine Nassif, Principal Engineer for Sapphire Rapids at Intel, the die size is a little lower than 400 mm² and the transistor count is between 11 and 12 billion."

Where did the 26 billion transistors in RaptorLake-S come from?

Intel 7 is definitely not 100 MTr/mm2.

This information is wrong. A single Zen4 CCD (8 cores) has 6.57B transistors, how can a robust server processor only have 12B transistors? Genoa has 78.8B.

 

[AMDK11]

This information is wrong. A single Zen4 CCD (8 cores) has 6.57B transistors, how can a robust server processor only have 12B transistors? Genoa has 78.8B.

Let us assume that there are 11.5 billion transistors for 15 physical cores in almost 400 mm2.

SapphireRapids is 4x400 mm2, giving a total of 1600 mm2 and 46 billion transistors for physically 60 cores.

Genoa has 96 cores, i.e. 12 chiplets of 8 cores each + I/O chiplet.

Two 2x 71 mm2 dies and 6.57 billion transistors give a total of 142 mm2 for 16 cores (Zen 4) and 13.14 billion transistors + I/O chiplet.

 

[Denver]

Let us assume that there are 11.5 billion transistors for 15 physical cores in almost 400 mm2.

SapphireRapids is 4x400 mm2, giving a total of 1600 mm2 and 46 billion transistors for physically 60 cores.

Genoa has 96 cores, i.e. 12 chiplets of 8 cores each + I/O chiplet.

Two 2x 71 mm2 dies and 6.57 billion transistors give a total of 142 mm2 for 16 cores (Zen 4) and 13.14 billion transistors + I/O chiplet.

I can't believe these numbers because it would result in 33mTr/mm², in other words density equivalent to that offered by 14nm; The improved 10nm (Intel 7) should reach up to 100mTr/mm²

Can TSMC Maintain Their Process Technology Lead - SemiWiki

 

[AMDK11]

I can't believe these numbers because it would result in 33mTr/mm², in other words density equivalent to that offered by 14nm; The improved 10nm (Intel 7) should reach up to 100mTr/mm²


View attachment 335939
Can TSMC Maintain Their Process Technology Lead - SemiWiki

I'm sure the transistor density per mm2 is higher for SapphireRapids. Look at EmeraldRapids which has 2 chips with a total surface area similar to the 4 for SapphireRapids.

EmeraldRapids physically has 2x 33 cores for a total of 66 cores with LLC per single 5MB core instead of 1.875MB (SapphireRapids).

A large part of the SapphireRapids surface is the connections between the 4 chips.

SapphireRapids 4x 393.88 mm2 = 1575.52 mm2 (Intel 7)

EmeraldRapids 2x 763.03 mm2 = 1526.05 mm2 (Intel 7)

Intel Emerald Rapids Backtracks on Chiplets – Design, Performance & Cost

Competitive Analysis Considerations, Sapphire Rapids Stealthy Redesign

www.semianalysis.com