AMD to Build Zen 6 CCD on TSMC 3nm Process, Next-Gen cIOD and sIOD on 4nm

[petr88]

They will do whatever fits their server CPUs best, and 12-core CCDs seem probable. Otherwise you have a sIOD with a giant Infinite Fabric hub with 16+ links to CCDs, which I don't think is optimal.

Regarding node shrinking, what's the SRAM scaling factor in N3 and N2 nodes? If it's bad then 48 MB of L3 and all of L2 will be very costly.

SRAM on 2N is 11% smaller than on N3 this is very good when we was stuck from 5N on 0.021um

 

[freeagent]

Sweet, I am probably not going to run Zen 5, but for sure Zen 6.

 

[TumbleGeorge]

I presume Zen 6 is still 2 years away for release, if it still uses AM5 socket, it is a pity, I was expecting an increase in PciExpress lanes which would need a new socket.

Needs just to replace some of sloooow PCIe 3.0 in MB chipsets with PCIe 4.0&5.0. Including these 4x PCIe 4.0 lanes between MB chipsets and CPU I/O chiplet.

 

[Wirko]

It isn't the technology or products themselves they really need to nail down, it's the prices and marketing - specifically the launch. Products that reviewers can easily recommend will sell and build mindshare.

Using less power, being on the best node, being ultra efficient are less important. Not to say those things can't also help of course.

They somehow don't care if their CPUs don't sell well right after launch. That's still their chiplet-hoarding-for-epyc phase. A few months later, what you said in the second paragraph matters increasingly more.

 

[Mr_Engineer]

This is weird... It's a lot of effort to build a new IO die for the last release on AM5... Unless there are no IO die changes for AM6, and they can re-use this new die on that platform too? But I'd like to think that AM6 will be quad channel, and have a few more PCiE lanes so would also need a new IO die...

Not weird really. The current IOD in Zen4/Zen5 is 6nm and a bit large. Moving to 4nm would allow for improvements to the weak memory controller and iGPU while still making the same or size.

I would like to see the following:

CCD #1 : 8 performance cores at 6 GHz and 128MB of L3 on die and stacked underneath with hyperthreading

CCD #2 : 16 dense cores at 4.5 GHz and hyperthreading

iOD : Improved memory controller with 1:1 8000 MHz DDR5

Honestly I won't be surprised if all Desktop Zen 6 CPUs use stacked L3 3d cache. Meaning the upper layer having the CCD (with 12 or 16 cores, L1, and L2), while the bottom layer having all the L3 cache. This would allow for a small die size (on 3nm), more cores and L3 cache.

 

[igormp]

This is weird... It's a lot of effort to build a new IO die for the last release on AM5... Unless there are no IO die changes for AM6, and they can re-use this new die on that platform too? But I'd like to think that AM6 will be quad channel, and have a few more PCiE lanes so would also need a new IO die...

I believe they should be able to port over many of their IP blocks for the IOD over to an AM6 IOD.
If you think about it, Strix Halo has an IOD made exclusively for it. I think AM5 has a bigger market, so it doesn't seem that weird to put some effort on it.

 

[Rightness_1]

Not weird really. The current IOD in Zen4/Zen5 is 6nm and a bit large. Moving to 4nm would allow for improvements to the weak memory controller and iGPU while still making the same or size.

I know all that. But my question remains. Why would they go to the expense of creating a new IO die on the last gen of AM5? They needed it badly on Zen5.

 

[TheLostSwede]

Yes, i think it needs more PciExpress lanes, look at the MB with 2-3 M.2 ports attached to the chipset, and all connected to the Cpu with a 4 lane PciExpress 4, not even PciEx 5. Not to mention the aditional PciX lanes in the chipset.
So MB manufacturers resort to activating/deactivating ports when you plug a M.2 connected to the chipset, or Sata ports, or lanes shared between a PCiX slot-M.2.

32 lanes would be sufficient.

So what you're saying is, AMD needs a new chipset with PCIe 5.0 support and more lanes, not a new IOD?
Also, why do we want PCI-X in 2025?

 

[freeagent]

Put it all on a chip and let us choose our own lane configuration.

Cant be that hard..

 

[TheLostSwede]

At first place, why would you attach 3 M.2 drives to chipset when latency- and performance-wise it's much better option attaching them to CPU?

This has been tested and it makes next to no difference in 99% of applications.

 

[3valatzy]

Sweet, I am probably not going to run Zen 5, but for sure Zen 6.

Zen 3 is ok for the next 20 years, no need to hurry on another rebranded Zen, even less so on a useless DDR5/PCIe5 platform.

 

[freeagent]

Zen 3 is ok for the next 20 years, no need to hurry on another rebranded Zen, even less so on a useless DDR5/PCIe5 platform.

Man, you are so negative when it comes to hardware that does not suit you.

 

[TheLostSwede]

About the PCIe lanes
Current AMD MB's have very few slots. I would prefer the 5.0x16 be split into fixed x8 and 2 x4 slots (in x16 and x8 formfactors).
Fixed means that the slots will always have that many lanes. No dependent on what is plugged into the other slots.
No PCIe switches needed (which are expensive).
You can still plug SSD's into these slots using a card. The advantage is that these cards can have better cooling because there is more space.
This is more flexible and lets the user choose what to plug in and the x8 slots take up less space than M2 slots.
This way you can have 3 M2 at 5.0 speeds. The number of M2's connected to the chipset can be reduced and the lanes converted in some more x4 slots.
It would be nice if the chipset would be connected using 5.0

Motherboards don't have PCIe switches in the consumer space any more, thanks to bifurcation.
What you do need though are retimers/redrivers to ensure signal integrity, if that was what you were thinking of.
Those add a few bucks and we can't get away from those, unless we fundamentally change the motherboard design and stick the CPU in the middle of the motherboard, but even that won't solve the problem entirely.
x8x8x0 or x8x4x4 is common bifurcation operation, but your "fixed" operation wouldn't cost any less than how it's done today, where you can control if you want to use bifurcation or not, since that's a software/firmware feature.
So in other words, what you're asking for, is largely how it works, except the interface speed between the chipset and CPU.
In fact, some expensive motherboards does exactly what you're asking for with regards to the M.2 drives too.

 

[Punkenjoy]

There was another rumor about AMD using parallel instead of serial transmission between the chiplets in it's new mobile processors.
This lowers power-consumption and latency. And it might also allow of higher fabric frequencies which in turn allows running the RAM at higher frequencies while still at 1:1 with the fabric.
If the rumor is true it is likely that this will also be implemented in Zen6.
Combine this with CUDIMM support and we should see much higher DRAM frequencies and lower latencies (which is great for e.g. gaming).
Having lower powerdraw, epecially in idle, would also be very welcome for me.

This is not a rumors but it have been confirmed directly by AMD Engineer. Strix Halo use fanout interconnection like RDNA3 that allow way more wires on the substrate than what we currently have for current Desktop Zen CPU.

It use way less power and is also in sync with the memory speed. They say a Single CCD can use the full 256 bit bandwidth so that is a great increase over the current infinity fabrics. They say it's also lower latency but we need to considerate that LPDDR memory is higher latency than DDR.

If AMD go that way for Zen Desktop, that would be a big gain for Zen 6 because they would remove a lot of bottleneck of the current architecture.

 

[TumbleGeorge]

I know all that. But my question remains. Why would they go to the expense of creating a new IO die on the last gen of AM5? They needed it badly on Zen5.

It's easy for understanding. Access to lithography nodes that needs for the lowest price that is possible. Also and traditional behavior of companies, to leave any other reason to want to upgrade to the next generation of components. In addition, the cost reduction between the ZEN 4 and ZEN 5 platforms as well.

 

[Jtuck9]

As things stand right now AMD AM5 CPUs dont support clocked DDR5 RAM, maybe with new memory controller on Zen6 things may change. MSI hasnt offered mini ITX board on flagship chipset for quite sometime.

Hopefully X870 motherboards end up support CUDIMM but all I've heard back from support is "full CUDIMM support with all features may not be guaranteed", whatever that means?! I'm not sure supporting the reclock chip feature is as simple as a BIOS update? They would hopefully drop down the voltage and temps of my build in the future, but I suppose running 8000+ modules at 1:1 would be nice either way.

Apparently MSI have a high end X870 ITX board coming out later this year (Q2 I believe). Just how high end is yet to be seen.

 

[ymdhis]

This is good news, it looks like Zen 6 will be finally when I update for AM5. The crap I/O die is one of the reasons holding me back.

There were also rumours that AMD will experiment with 3d stacking on the I/O die. Either put extra memory on top of it to make the iGPU more powerful (think Strix Halo with crapton of cache), or even put the compute chiplets on top of the I/O for significantly reduced latency and power usage.

 

[Wirko]

I know all that. But my question remains. Why would they go to the expense of creating a new IO die on the last gen of AM5? They needed it badly on Zen5.

Because they expect good sales? Because Zen 6 might not be the last generation on AM5? The socket will stay alive for as long as DDR5 and PCIe stay alive and current, which possibly means Zen 7. Or maybe Zen 6+ if AMD does some sort of refresh in between.

or even put the compute chiplets on top of the I/O for significantly reduced latency and power usage.

This would make room for two stacks of LPDDR6-9600, haha. And we would be able to compare apples to Apple's.

 

[10tothemin9volts]

I was hoping for 12-core CCDs for Zen 5 (also due to the 2x8-core X3D thing). Now I'm hoping for 12-core or 16-core CCDs for Zen 6 + the usual ~30% power efficiency improvement, though Zen 5 9800X3D has a worse power efficiency than my Zen 4 7800X3D, by like 30% in some cases (due to higher clocks).

The company's next-generation discrete GPUs will be built around the TSMC N3E foundry node.

Of course it's gonna be TSMC N3E or N3P? Though in 2 years maybe there's a small chance it could be TSMC N2 1st generation, but probably APPLE will use it first, as always.

I wish AMD would introduce AM6 with Zen 6 and DDR6 (=higher bandwidth -> faster token/s for local LLM hosting + quad channel in consumer segment), but yeah, ppl would complain that only 2 generations would be supported by AM5, also DDR6 isn't gonna be ready by then.

 

[3valatzy]

Of course it's gonna be TSMC N3E or N3P? Though in 2 years maybe there's a small chance it could be TSMC N2 1st generation, but probably APPLE will use it first, as always.

Apple has been using it for at least half a year already. It even has results from the initial trial runs - 60% yields which is not bad at all.

TSMC hits 60% yield on 2nm chip trial production

The semiconductor giant is primed for mass production in 2025. TSMC has successfully conducted a trial chip production of its 2nm N2 process with a 60%...

www.gsmarena.com

TSMC begins small-scale trial production of 2nm chips, mass production set for 2025 - SemiMedia

www.semimedia.cc

I wish AMD would introduce AM6 with Zen 6 and DDR6 (=higher bandwidth -> faster token/s for local LLM hosting + quad channel in consumer segment), but yeah, ppl would complain that only 2 generations would be supported by AM5, also DDR6 isn't gonna be ready by then.

DDR6 is useless for at least 5 years to come. We haven't reached the highs of DDR5 - which are DDR5-10000 or so.

My desktop lives happily with DDR4-3200.
While my mobile with just DDR5-7500.

 

[TumbleGeorge]

DDR6 is useless for at least 5 years to come

Do you bet on this?

 

[alawadhi3000]

Apple has been using it for at least half a year already. It even has results from the initial trial runs - 60% yields which is not bad at all.

TSMC hits 60% yield on 2nm chip trial production

The semiconductor giant is primed for mass production in 2025. TSMC has successfully conducted a trial chip production of its 2nm N2 process with a 60%...

www.gsmarena.com

Saying that a process has 60% yield is useless without knowing the die size.

 

[PashkaTLT]

I have conflicting thoughts on this subject.
On the other hand, I respect AMDs long support for AM5. That's some great design of the CPUs & the socket.
On the other hand, as you mentioned, would be nice to have faster PCIe lanes or more of them.
Yes, few people need so many lanes, but I'm one of them with my 5 x M2 SSDs...

 

[Rightness_1]

Saying that a process has 60% yield is useless without knowing the die size.

Don't they usually make a memory die as a trial? A 60% yield is not spectacular on making the easiest to produce silicon die known to man... So it must be a long way from being viable to make a complex chip like a GPU/CPU.