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Huawei recently revealed that its CloudMatrix 384 AI super node cluster can outperform NVIDIA's GB200 NVL72 in standard benchmarks, even though it consumes more power per performance unit. That system relies on Huawei's current Ascend 910C accelerators, which deliver strong raw compute performance but lag behind in efficiency metrics. To address this gap, Huawei is preparing the Ascend 920 family, with the training‑focused Ascend 920C built on SMIC's 6 nm process. According to DigiTimes, each 920C card will deliver more than 900 TeraFLOPS of BF16 half-precision performance. It also upgrades memory to HBM3 modules, providing 4,000 GB/s of bandwidth, which is up from the Ascend 910C's eight HBM2E stacks and 3,200 GB/s.
The existing Ascend 910C peaks at 780 TeraFLOPS in BF16 operations and uses a chip‑to‑chip interconnect bandwidth of 400 GB/s. Its packaging limits that bandwidth, but it still supports high‑speed communication between nodes in ultra‑dense AI clusters. Huawei will retain the chiplet‑based design in the 920C and refine the tensor acceleration engines for Transformer and Mixture‑of‑Experts models. Internal projections estimate that overall training efficiency on the 920C will improve by 30-40 percent compared to the 910C. This should narrow the performance‑per‑watt difference against competitors' solutions. In terms of system integration, the Ascend 920C will support PCIe 5.0 and next‑generation high‑throughput interconnect protocols. These features aim to improve resource scheduling and reduce latency in super node deployments, where tight node‑to‑node synchronization is critical. Huawei has not announced a firm release date for the Ascend 920C, but DigiTimes sources claim that it will enter mass production in the second half of 2025, which could mean just a few months from now.
View at TechPowerUp Main Site | Source
The existing Ascend 910C peaks at 780 TeraFLOPS in BF16 operations and uses a chip‑to‑chip interconnect bandwidth of 400 GB/s. Its packaging limits that bandwidth, but it still supports high‑speed communication between nodes in ultra‑dense AI clusters. Huawei will retain the chiplet‑based design in the 920C and refine the tensor acceleration engines for Transformer and Mixture‑of‑Experts models. Internal projections estimate that overall training efficiency on the 920C will improve by 30-40 percent compared to the 910C. This should narrow the performance‑per‑watt difference against competitors' solutions. In terms of system integration, the Ascend 920C will support PCIe 5.0 and next‑generation high‑throughput interconnect protocols. These features aim to improve resource scheduling and reduce latency in super node deployments, where tight node‑to‑node synchronization is critical. Huawei has not announced a firm release date for the Ascend 920C, but DigiTimes sources claim that it will enter mass production in the second half of 2025, which could mean just a few months from now.
View at TechPowerUp Main Site | Source
