NVIDIA RTX PRO 6000 GDDR7 Memory Comes in 3 GB Modules, Sandwiching the PCB on Both Sides

[AleksandarK]

NVIDIA has significantly advanced professional graphics by rebranding its workstation lineup as "RTX PRO" and incorporating an amazing 96 GB of GDDR7 memory capacity into a single RTX PRO 6000 card. This marks the first time 3 GB GDDR7 modules have been employed in a workstation GPU, each supporting error-correcting code for enhanced reliability. By arranging 16 such modules on each side of the PCB, NVIDIA achieves the remarkable 96 GB capacity while maintaining a TDP limit of 300 W for its Max-Q variant (pictured below) and up to 600 W for other SKUs. A recent leak on the Chiphell forum provides a clear insight into the new PCB layout. The customary 12 V-6×2 power connector has been omitted and replaced by four solder points intended for a cable extension.

This design choice suggests preparation for both Server and Max-Q editions, where power inputs are relocated to the rear of the card. Despite the simplified power interface and reduced footprint, the Max-Q model retains the full GB202 Blackwell GPU and the complete memory capacity. At the top of the series, the RTX PRO 6000 Blackwell will be offered in three distinct configurations. The Workstation and Server editions feature 24,064 CUDA cores, 96 GB of GDDR7 ECC memory, and a 600 W power budget, ensuring consistent performance in desktop towers and rack-mounted systems. The Max-Q edition employs the identical GPU and memory configuration but limits power consumption to 300 W through lower clocks and power limits, making it particularly well suited for compact chassis and noise-sensitive environments.




NVIDIA also intends to extend the RTX PRO architecture to its midrange offerings. The RTX PRO 5000 will utilize the same dual-sided board, populating only one side to deliver 48 GB of memory. This modular strategy allows NVIDIA to maximize component reuse and expedite development across multiple product tiers. The company is also currently exploring making GeForce RTX 5080 SUPER and RTX 5070 SUPER with additional memory capacity, coming with 24 GB (8×3 GB) and 18 GB (6×3 GB) memory, respectively.

View at TechPowerUp Main Site | Source

 

[Wirko]

What does ECC in GDDR7 look like? In-band, out-of-band, CRC, how many bits?

The only details I can find and understand are on-die ECC (as in DDR5) and CA parity. CA is probably the command and address bus, I'm not sure if any other type of memory employs that.

Source: Micron GDDR7 product brief

Edit: some discussion at our home too:

How GDDR7 works compared to GDDR6

Hello everyone, I'm making this post because following the RTX 5090 launch I was confused about how exactly GDDR7 operates, especially in the PAM3 encoding mode which is used in Blackwell. I've done some reading, and I believe I'm prepared to explain for those of you who are interested, but part...

www.techpowerup.com

 

[Nostras]

If 3GB chips become more commonplace that would reduce the prices of them as well, meaning next gen we will probably get a 6060 with 12GB of VRAM on a 128 bit bus.
Or, at least Nvidia can't pull their "3GB chips are too expensive" card out of their ass.

 

[Denver]

If 3GB chips become more commonplace that would reduce the prices of them as well, meaning next gen we will probably get a 6060 with 12GB of VRAM on a 128 bit bus.
Or, at least Nvidia can't pull their "3GB chips are too expensive" card out of their ass.

"Oh, Boy... You say 12GB, but I see 9GB. let's start humble here." — Jensen, Leather man

 

[AleksandarK]

What does ECC in GDDR7 look like? In-band, out-of-band, CRC, how many bits?

The only details I can find and understand ar on-die ECC (as in DDR5) and CA parity. CA is probably the command and address bus, I'm not sure if any other type of memory employs that.

Source: Micron GDDR7 product brief

Edit: some discussion at our home too:

How GDDR7 works compared to GDDR6

Hello everyone, I'm making this post because following the RTX 5090 launch I was confused about how exactly GDDR7 operates, especially in the PAM3 encoding mode which is used in Blackwell. I've done some reading, and I believe I'm prepared to explain for those of you who are interested, but part...

www.techpowerup.com

I thought aboug this too, but I have to dig deeper there.

 

[Nostras]

"Oh, Boy... You say 12GB, but I see 9GB. let's start humble here." — Jensen, Leather man

That would require a 96-bit memory bus. Do these still exist?
Edit: https://www.techpowerup.com/gpu-specs/?buswidth=96 bit&sort=released
Not really, but don't tell Jensen lol.

 

[Panther_Seraphin]

That would require a 96-bit memory bus. Do these still exist?
Edit: https://www.techpowerup.com/gpu-specs/?buswidth=96 bit&sort=released
Not really, but don't tell Jensen lol.

Where do you think those defective 5060 dies are going to end up?

 

[TSiAhmat]

That would require a 96-bit memory bus. Do these still exist?
Edit: https://www.techpowerup.com/gpu-specs/?buswidth=96 bit&sort=released
Not really, but don't tell Jensen lol.

can't you just not populate one of the slots? Similar to 1080ti 11GB & 3080 10GB (as an example)

 

[Caring1]

So when are they bring back the Graphics Cards with NVMe slots on the back so the end user can increase volatile memory?

 

[TSiAhmat]

So when are they bring back the Graphics Cards with NVMe slots on the back so the end user can increase volatile memory?

maybe after the AI bubble bursts ^^" Would be a huge problem for AI margin (at least I assume it would be)

 

[ncrs]

What does ECC in GDDR7 look like? In-band, out-of-band, CRC, how many bits?

The only details I can find and understand are on-die ECC (as in DDR5) and CA parity. CA is probably the command and address bus, I'm not sure if any other type of memory employs that.

Source: Micron GDDR7 product brief

Edit: some discussion at our home too:

How GDDR7 works compared to GDDR6

Hello everyone, I'm making this post because following the RTX 5090 launch I was confused about how exactly GDDR7 operates, especially in the PAM3 encoding mode which is used in Blackwell. I've done some reading, and I believe I'm prepared to explain for those of you who are interested, but part...

www.techpowerup.com

On consumer-derived designs, so on GDDR, ECC is in-band, single bit correction and double bit detection. It decreases the available VRAM by ~6.25% and decreases maximum memory bandwidth, so for example a 48GB L40 which is an AD102 will only have 46068MiB available VRAM with ECC enabled which is the default. This can be disabled at the driver level, but requires a reboot, so the "lost" VRAM can be used when ECC isn't required.

HBM designs have proper out-of-band ECC without performance impact. They also have advanced recovery features like error containment (only the process using affected memory area is terminated/restarted when uncorrectable event occurs), page offlining (disablement of the area affected - HBM chips have spare area to accommodate this just like SSDs) and on some Blackwell HBM channel repair.

 

[GenericUsername2001]

That would require a 96-bit memory bus. Do these still exist?
Edit: https://www.techpowerup.com/gpu-specs/?buswidth=96 bit&sort=released
Not really, but don't tell Jensen lol.

Laptop 4050s & the desktop 6 GB Geforce 3050 use a 96 bit bus, and those are rather common in new products. (Not that I would recommend either of them, mind you.)