NEO Semiconductor Unveils Breakthrough 1T1C and 3T0C IGZO-Based 3D X-DRAM Technology

[TheLostSwede]

NEO Semiconductor, a leading developer of innovative technologies for 3D NAND flash memory and 3D DRAM, announced today the latest advancement in its groundbreaking 3D X-DRAM technology family—the industry-first 1T1C- and 3T0C-based 3D X-DRAM cell, a transformative solution designed to deliver unprecedented density, power efficiency, and scalability for the most demanding data applications.

Built on a 3D NAND-like architecture and with proof-of-concept test chips expected in 2026, the new 1T1C and 3T0C designs combine the performance of DRAM with the manufacturability of NAND, enabling cost-effective, high-yield production with densities up to 512 Gb—a 10x improvement over conventional DRAM.
"With the introduction of the 1T1C and 3T0C 3D X-DRAM, we are redefining what's possible in memory technology," said Andy Hsu, Founder & CEO of NEO Semiconductor. "This innovation pushes past the scaling limitations of today's DRAM and positions NEO as a frontrunner in next-generation memory."




Key Features and Benefits:

• Unmatched Retention and Efficiency - Thanks to IGZO channel technology, 1T1C and 3T0C cell simulations demonstrate retention times of up to 450 seconds, dramatically reducing refresh power.
• Verified by Simulation - TCAD (Technology Computer-Aided Design) simulations confirm fast 10-nanosecond read/write speeds and over 450-second retention time.
• Manufacturing-Friendly - Uses a modified 3D NAND process, with minimal changes, enabling full scalability and rapid integration into existing DRAM manufacturing lines.
• Ultra-High Bandwidth - Employs unique array architectures for hybrid bonding to significantly enhance memory bandwidth while reducing power consumption.
• High Performance for Advanced Workloads - Designed for AI, edge computing, and in-memory processing, with reliable high-speed access and reduced energy consumption.

Expanding the 3D X-DRAM Family:
NEO Semiconductor's technology platform now includes three 3D X-DRAM variants:

• 1T1C (one transistor, one capacitor) - The core solution for high-density DRAM, fully compatible with mainstream DRAM and HBM roadmaps.
• 3T0C (three transistor, zero capacitor) - Optimized for current-sensing operations, ideal for AI and in-memory computing.
• 1T0C (one transistor, zero capacitor) - A floating-body cell structure suitable for high-density DRAM, in-memory computing, hybrid memory and logic architectures.

NEO Semiconductor will attend the 17th IEEE International Memory Workshop, May 18th-21st 2025 in Monterey, CA, USA.

View at TechPowerUp Main Site | Source

 

[user556]

Useless picture. Channel and dielectric marked as the same layer, and nothing else marked at all.

 

[TheLostSwede]

Useless picture. Channel and dielectric marked as the same layer, and nothing else marked at all.

Did you bother going to their website?

3d X-DRAM - Neo Semiconductor | X-Nand

3D X-DRAMTM World’s First 3D NAND-like DRAM 3D X-DRAM is a game-changing technology for DRAM, leveraging a 3D NAND-like cell structure to achieve remarkable density, power efficiency, and scalability. Three innovative generations of cells leverage a modified 3D NAND flash process, significantly...

neosemic.com

 

[user556]

Yes ... but that doesn't change the fact that TPU's posted image is useless.

Here's the relevant diagram from their whitepaper:

"Capacitor Plate" is the GND connect in the schematic on the right.

 

[TheLostSwede]

Yes ... but that doesn't change the fact that TPU's posted image is useless.

Sorry? That was what the company provided with the press release.

Here's the relevant diagram from their whitepaper:
View attachment 398577

"Capacitor Plate" is the GND connect in the schematic on the right.

And that is my fault somehow? I can't control if companies f-up, I didn't draw the picture.

 

[Wirko]

If there's any possibility of making it QLC, they will make it QLC.

 

[user556]

If there's any possibility of making it QLC, they will make it QLC.

This is DRAM type tech, not Flash. It has a sloping discharge in milliseconds, not centuries. And DRAM's slope is traditionally very temperature sensitive with hot dies needing much higher refresh.

PS: I guess multilevel cells is not impossible but, given that "Rowhammer" like vulnerabilities are already making DRAM precarious as is, it would seem impractical to me.

Access time suffers too. That matters more for DRAM than Flash.

Sorry? That was what the company provided with the press release.

Maybe they need some prompting about who they're feeding. Techie websites expect techie details.

 

[Wirko]

This is DRAM type tech, not Flash. It has a sloping discharge in milliseconds, not centuries. And DRAM's slope is traditionally very temperature sensitive with hot dies needing much higher refresh.

PS: I guess multilevel cells is not impossible but, given that "Rowhammer" like vulnerabilities are already making DRAM precarious as is, it would seem impractical to me.

Access time suffers too. That matters more for DRAM than Flash.

It was done experimentally many years ago. If NEO really extended the necessary refresh interval to 450 s for 1-bit cells, multi-level certainly becomes a possibility. And for storing AI model weights, analog memory also becomes a realistically usable option.

https://www.eetimes.com/nec-experiments-in-multi-level-cells-for-drams/

 

[user556]

Wow, 27 years ago! I guess that proves there was a reliability problem. And long before Rowhammer became a known issue too.