PCI-SIG Releases PCIe 7.0 Specification to Support 128.0 GT/s Transfer Rates

[Nomad76]

PCI-SIG today announced the official release of the PCI Express (PCIe) 7.0 specification, reaching 128.0 GT/s, to members. PCIe 7.0 specification targets data-driven applications like AI/ML, 800G Ethernet, cloud, and Quantum computing. Pathfinding for the PCIe 8.0 specification is already in progress to continue supporting the industry's investments and product roadmaps in the PCIe technology ecosystem.

PCIe 7.0 Specification Features

• Delivers 128.0 GT/s raw bit rate and up to 512 GB/s bi-directionally via x16 configuration
• Utilizes PAM4 (Pulse Amplitude Modulation with 4 levels) signaling and Flit-based encoding
• Provides improved power efficiency
• Maintains backwards compatibility with previous generations of PCIe technology

"PCIe technology has served as the high-bandwidth, low-latency IO interconnect of choice for over two decades and we are pleased to announce the release of the PCIe 7.0 specification, which continues our long-standing tradition of doubling the IO bandwidth every three years," said Al Yanes, PCI-SIG President and Chairperson. "As artificial intelligence applications continue to scale rapidly, the next generation of PCIe technology meets the bandwidth demands of data-intensive markets deploying AI, including hyperscale data centers, high performance computing (HPC), automotive and military/aerospace."

"It's a special occasion when a PCIe specification hits the final version," observed Ian Cutress, Chief Analyst and CEO, More Than Moore. "The rise in the demand for both compute and networking, enabled through PCIe technology, is at an all-time high, despite the complexities of creating standards in the industry around high-speed signaling. Datacenters are ready to start deploying networks built on PCIe 7.0 technology, and almost every ASIC company I talk to is already engaged with the IP providers and are set to take advantage. Even with the popularity and focus that went into PCIe 6.0 deployment, the PCIe 7.0 specification has more enthusiasm than any previous version."

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[Bobaganoosh]

(I remembered after posting this gif that you're not supposed to just post a gif or picture as a reply without some kind of comment)...well...cool. I haven't even seen PCIe 6 in the world yet, but now we have 7.0. I guess they have to release the spec before we can use it, but it sometimes seems wild when we're not even utilizing a couple gens ago in the mainstream.

 

[Battler624]

Am I wrong or are the numbers exactly twice what they should be?

Isn't PCIE 4, at 4 lanes, 8GB/s?

 

[LabRat 891]

Meanwhile, PCB designers

 

[TumbleGeorge]

Isn't PCIE 4, at 4 lanes, 8GB/s?

Yes in one direction. But marketing sum speed in two directions.

 

[PrEzi]

Wonder how long can be the lines without retimers. With 5.0 it was already an issue, with 6.0 I have seen no improvements, so I assume 7.0 vs 5.0 would need at least 30 if not 50% more redrivers/retimers on the lines (making the whole even more costly). Wonder how big of a role the optical part would play here... which was kinda missed here in the announcement ?

 

[umeng2002]

Damn, I'm still on 4.0. My wife is going to leave me, and my colleagues at work are going to laugh at me.

 

[Mysteoa]

Damn, I'm still on 4.0. My wife is going to leave me, and my colleagues at work are going to laugh at me.

I'm still on 3.0

 

[Nomad76]

Wonder how long can be the lines without retimers. With 5.0 it was already an issue, with 6.0 I have seen no improvements, so I assume 7.0 vs 5.0 would need at least 30 if not 50% more redrivers/retimers on the lines (making the whole even more costly). Wonder how big of a role the optical part would play here... which was kinda missed here in the announcement ?

The optical interconnectivity is going to be a must, even with PCIe 6.0, there are already some of the big-names working on possible solutions. We did cover that area in the past with news (just some recent examples below). To summarize, optical (at least on "industrial/enterprise" areas) is a must. For mortals like us, it's not viable.

Marvell Demonstrates Industry's First End-to-End PCIe Gen 6 Over Optics at OFC 2025

Marvell Technology, Inc., a leader in data infrastructure semiconductor solutions, today announced in collaboration with TeraHop, a global optical solutions provider for AI driven data centers, the demonstration of the industry's first end-to-end PCIe Gen 6 over optics in the Marvell booth #2129...

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NVIDIA Commercializes Silicon Photonics with InfiniBand and Ethernet Switches

NVIDIA has developed co-packaged optics (CPO) technology with TSMC for its upcoming Quantum-X InfiniBand and Spectrum-X Ethernet switches, integrating silicon photonics directly onto switch ASICs. The engineering approach reduces power consumption by 3.5x. It decreases signal loss from 22 dB to...

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STMicroelectronics Enhances Optical Interconnects for Faster AI and Cloud Datacenters

STMicroelectronics, a global semiconductor leader serving customers across the spectrum of electronics applications, is unveiling its next generation of proprietary technologies for higher-performing optical interconnect in datacenters and AI clusters. With the exponential growth of AI computing...

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Ayar Labs Unveils World's First UCIe Optical Chiplet for AI Scale-Up Architectures

Ayar Labs, the leader in optical interconnect solutions for large-scale AI workloads, today announced the industry's first Universal Chiplet Interconnect Express (UCIe) optical interconnect chiplet to maximize AI infrastructure performance and efficiency while reducing latency and power...

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[bonehead123]

Damn, I'm still on 4.0. My wife is going to leave me, and my colleagues at work are going to laugh at me.

Well, my wife said that if I didn't immediately start using pcie-12xxx, she was gonna leave me too....

So I did, & she didn't, so all is good here, hehehehe

As for my cowerkers, I can just say "F" them, since I work remotely, I don't really give a rat's ass what they say about me around the office, cause I know NONE of them have the balls to say anything to my face, which they only see like once every 45-60 days, and they know I would fire their collective asses in a friggin heartbeat if they did say something stupid to me !

But back on topic.......yeehaw to the pci-e folks, now gimme v12 or gimme death..

 

[PrEzi]

The optical interconnectivity is going to be a must, even with PCIe 6.0, there are already some of the big-names working on possible solutions. We did cover that area in the past with news (just some recent examples below). To summarize, optical (at least on "industrial/enterprise" areas) is a must. For mortals like us, it's not viable.

Marvell Demonstrates Industry's First End-to-End PCIe Gen 6 Over Optics at OFC 2025

Marvell Technology, Inc., a leader in data infrastructure semiconductor solutions, today announced in collaboration with TeraHop, a global optical solutions provider for AI driven data centers, the demonstration of the industry's first end-to-end PCIe Gen 6 over optics in the Marvell booth #2129...

www.techpowerup.com

NVIDIA Commercializes Silicon Photonics with InfiniBand and Ethernet Switches

NVIDIA has developed co-packaged optics (CPO) technology with TSMC for its upcoming Quantum-X InfiniBand and Spectrum-X Ethernet switches, integrating silicon photonics directly onto switch ASICs. The engineering approach reduces power consumption by 3.5x. It decreases signal loss from 22 dB to...

www.techpowerup.com

STMicroelectronics Enhances Optical Interconnects for Faster AI and Cloud Datacenters

STMicroelectronics, a global semiconductor leader serving customers across the spectrum of electronics applications, is unveiling its next generation of proprietary technologies for higher-performing optical interconnect in datacenters and AI clusters. With the exponential growth of AI computing...

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Ayar Labs Unveils World's First UCIe Optical Chiplet for AI Scale-Up Architectures

Ayar Labs, the leader in optical interconnect solutions for large-scale AI workloads, today announced the industry's first Universal Chiplet Interconnect Express (UCIe) optical interconnect chiplet to maximize AI infrastructure performance and efficiency while reducing latency and power...

www.techpowerup.com

I am wondering why are you so defensive... In the past few months you have covered some of the optical tech based on the old spec (I assume pre 6.4 ?). True.
But no word on how PCI-SIGs Optical Aware Retimer Engineering Change Notice (ECN) amends the PCIe 6.4 specification and the new PCIe 7.0 specification to include a PCIe (optical) retimer-based solution.
Might not be important for consumers.... but we will see.... Maybe fibre on the mainboard would be cheaper for the end consumer too, if too many standard retimers need to be included to warrant a clean signaling across the mainboard.

 

[Nomad76]

I am wondering why are you so defensive... In the past few months you have covered some of the optical tech based on the old spec (I assume pre 6.4 ?). True.
But no word on how PCI-SIGs Optical Aware Retimer Engineering Change Notice (ECN) amends the PCIe 6.4 specification and the new PCIe 7.0 specification to include a PCIe (optical) retimer-based solution.
Might not be important for consumers.... but we will see.... Maybe fibre on the mainboard would be cheaper for the end consumer too, if too many standard retimers need to be included to warrant a clean signaling across the mainboard.

Not being defensive at all

"The PCI-SIG Optical Work Group is exploring an optical interconnect supporting a wide range of optical technologies to make PCIe architecture more optical friendly. Additional information will be available soon." via PCI-SIG https://pcisig.com/faq?field_category_value[]=pci_express_7.0&keys=

 

[anonuser57]

Wonder how long can be the lines without retimers. With 5.0 it was already an issue, with 6.0 I have seen no improvements, so I assume 7.0 vs 5.0 would need at least 30 if not 50% more redrivers/retimers on the lines (making the whole even more costly). Wonder how big of a role the optical part would play here... which was kinda missed here in the announcement ?

PAM4 signaling starting in pcie 6.0. Hopefully that enables higher bandwidth at the same frequency. If all goes well we will see motherboards with pcie 6 slots that can't do pcie 5 but can still do pcie 4.

 

[Roph]

I can see it already, an RTX 8060 (that's actually the tiny 8030-class chip) with an x4 PCIe interface.

 

[lexluthermiester]

We're barely using PCIe 5.0 Really with PCIe 7.0?

 

[Crackong]

Signal integrality

 

[sLowEnd]

We're barely using PCIe 5.0 Really with PCIe 7.0?

The standards are set years before products appear, to allow time for product development. PCI-E 6.0 was finalized in 2022, but we aren't seeing consumer products that utilize it yet.

 

[AsRock]

Wonder how long can be the lines without retimers. With 5.0 it was already an issue, with 6.0 I have seen no improvements, so I assume 7.0 vs 5.0 would need at least 30 if not 50% more redrivers/retimers on the lines (making the whole even more costly). Wonder how big of a role the optical part would play here... which was kinda missed here in the announcement ?

Driving costs up for gamer's that's for sure, just don't need it.

 

[lexluthermiester]

The standards are set years before products appear, to allow time for product development. PCI-E 6.0 was finalized in 2022, but we aren't seeing consumer products that utilize it yet.

Yeah, I get that. but PCIe 6.0 isn't even in the workstation space yet, let alone the consumer space. Planning ahead is always a good idea, but this far ahead?

 

[A Computer Guy]

Meanwhile, PCB designers

Maybe then we'll start getting those tiny STX motherboards with a PCIe 7.0 GPU slot edge connector. The traces will be nice and short for great signal integrity.

Driving costs up for gamer's that's for sure, just don't need it.

They'll find some way for AI to use it. You'll get a PCIe 7.0 M.2 for ultra fast local AI storage.

 

[igormp]

We're barely using PCIe 5.0 Really with PCIe 7.0?

Enterprise market is really demanding faster interconnects, see NVLink and UALink, as well as new products on top of CXL being a thing now.

The cadence for new PCIe revisions has been shortening over time.
- 4.0 had its preliminary spec in 2011, final spec in 2017, and first products making use of it in 2017~2018.
- 5.0 had its preliminary spec in 2017, final spec in 2019, and the first devices in 2020.
- 6.0 had its preliminary spec in 2020, final spec in 2022, and the first devices are finally appearing this year. Blackwell in theory is PCIe 6.0 capable, but afaik the certification for that is not available yet.
- 7.0 had its preliminary spec in 2024, and we're seeing the final spec now, so I assume we will only be seeing devices on top of it by 2027 or so.

Enterprise adoption for 6.0 should happen plenty fast once the certifications are finally available, and hopefully 7.0 shouldn't take as long to become a thing.

 

[Rightness_1]

And they can't even get PCiE 5.0 right still!

 

[mroofie]

Many still stuck on pcie 3 and here comes pcie 7

 

[dyonoctis]

Yeah, I get that. but PCIe 6.0 isn't even in the workstation space yet, let alone the consumer space. Planning ahead is always a good idea, but this far ahead?

Don't forget that they are already working on PCIe 8.0 .

A.I isn't going to become sentient and purge the world if the engineers aren't zealous like that

 

[TumbleGeorge]

Don't forget that they are already working on PCIe 8.0 .

A.I isn't going to become sentient and purge the world if the engineers aren't zealous like that

Don't cry my friend. We like home users may didn't get even PCIe 6.0 SSD before 2030. Not sure from when will have PCIe 6.0 slot on motherboards, but for SSD must be patient or must buy industrial SSD.