AMD Sampling Next-Gen Ryzen Desktop "Medusa Ridge," Sees Incremental IPC Upgrade, New cIOD

[btarunr]

AMD is reportedly sampling its next-generation Ryzen desktop processor powered by the "Zen 6" microarchitecture, codenamed "Medusa Ridge," to close industry partners, such as platform designers and OEMs, says Yuri Bubliy, aka 1usmus, author of the Hydra tuning software, and the now-retired DRAM Calculator for Ryzen. The processor sees AMD update both the CCDs and client I/O die, he says. AMD confirmed that it is building the "Zen 6" CCD on the TSMC N2 (2 nm) node, which entered risk production earlier this year. The node is expected to be ready for mass-production of 2 nm chips later this year. The 2 nm node presents a significant jump in transistor densities from the current TSMC N4P node on which AMD builds its 8-core "Zen 5" CCD, which 1usmus and other sources say, that AMD will use to increase CPU core counts per CCD.

Sources point to the possibility of AMD increasing core counts per CCD to 12, and giving the CCD 48 MB of L3 cache. At this point we don't know if all 12 cores will be arranged in a single CCX with a monolithic slab of 48 MB L3 cache, or if there's a dual-CCX layout with 6 cores per CCX sharing 24 MB of L3 cache, each. The other big upgrade with "Medusa Ridge" is its client I/O die (cIOD). AMD is expected to build its new generation cIOD on a newer EUV node such as 5 nm N5 or 4 nm N4P, a significant upgrade from the current 6 nm N6. 1usmus says that the biggest reason for AMD to update its cIOD is the memory controller architecture. AMD is expected to give "Medusa Point" a new dual memory controller architecture. There are still two DDR5 channels per socket, but this is redesigned for increased memory speeds, letting AMD catch up with Intel in this area. As for the CPU frequency boosting technologies, such as PBO and Curve Optimizer, there are no updates expected, and 1usmus concludes that it Hydra support should be straightforward.



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[ZoneDymo]

Looking forward to it, would be nice if the consumers get a bump in core count again, we have had 16 core 32 thread parts since Ryzen 3000.

 

[john_]

new dual memory controller architecture

I wish one controller being DDR5 and the other GDDR6. That could be useful for APUs. AMD needs to create something new, like for example add a memory slot on motherboards, something that looks like a sodimm slot for example, that can take custom GDDR6 memory modules. That could offer all the bandwidth those iGPUs need to shine while living the bandwidth from DDR5 dimms all to the CPU.

 

[Rabit]

Zen 6 points that interest me Ryzen 5 at 8 cores, +50% L3 = 48mb , 10x more connections between CCD and CCX, Ram latency on pair with monolith design + faster ram support, all this will lead to very noticeable gaming performance improvement.
Bonus X3D get 96mb +48mb for 144mb total L3 this is 50% more than 9800X3D

 

[dyonoctis]

I wish one controller being DDR5 and the other GDDR6. That could be useful for APUs. AMD needs to create something new, like for example add a memory slot on motherboards, something that looks like a sodimm slot for example, that can take custom GDDR6 memory modules. That could offer all the bandwidth those iGPUs need to shine while living the bandwidth from DDR5 dimms all to the CPU.

From my understanding, the type of chip isn't really the issue, but rather the interface. High bandwidth need more traces, and high quality traces at that. Motherboards traces were part of the limitations preventing four dimms of DDR5 from running at XMP/EXPO speed.

 

[holyprof]

Looking forward to it, would be nice if the consumers get a bump in core count again, we have had 16 core 32 thread parts since Ryzen 3000.

I was getting enthusiastic too, but I'm not sure AMD is willing to give regular desktop users more than 32 threads and erode their Threadripper family.
I hope for the 12-core single CCX CPU though, to replace my aging 8 core 3700X.

 

[Rabit]

From my understanding, the type of chip isn't really the issue, but rather the interface. High bandwidth need more traces, and high quality traces at that. Motherboards traces were part of the limitations preventing four dimms of DDR5 from running at XMP/EXPO speed.

Quad channel will required at-least 40% more pads and bigger CPU socket, traces issue can be solved by placing 2 CAMM like slot on back side of PCB where CPU socket is placed, to have shortest route from CPU.

 

[Hecate91]

I'm looking forward to a single 12 core CCD, also would be interesting if AMD can double the Infinity Fabric speed with dual memory controllers.

 

[Nhonho]

Looking forward to it, would be nice if the consumers get a bump in core count again, we have had 16 core 32 thread parts since Ryzen 3000.

I prefer an 8-core CPU with higher IPC per core. And with no E-cores.

Desktop apps need CPUs with high IPC per core, not CPUs with dozens of weak cores.

 

[TheinsanegamerN]

I prefer an 8-core CPU with higher IPC per core. And with no E-cores.

Desktop apps need CPUs with high IPC per core, not CPUs with dozens of weak cores.

Why limit yourself? Mobile Ryzen has 12 core CCDs.

Also, please learn what an E core is, and what a ryzen C core is. These are not the same thing.

Quad channel will required at-least 40% more pads and bigger CPU socket, traces issue can be solved by placing 2 CAMM like slot on back side of PCB where CPU socket is placed, to have shortest route from CPU.

CAMM2 modules are having the same signal integrity issues that DIMM modules have trying to push past 6000 mhz.

I wish one controller being DDR5 and the other GDDR6. That could be useful for APUs. AMD needs to create something new, like for example add a memory slot on motherboards, something that looks like a sodimm slot for example, that can take custom GDDR6 memory modules. That could offer all the bandwidth those iGPUs need to shine while living the bandwidth from DDR5 dimms all to the CPU.

It'd be a lot easier to simply put a x3d cache on their APUs instead of another memory controller. Not to mention that a triple bus system is going to be significantly more expensive for the end consumer than a dual pus system like we have now.

 

[Visible Noise]

Has AMD ever announced tape out of Zen6? Otherwise this is typical WCCF garbage.

 

[Launcestonian]

Quad channel will required at-least 40% more pads and bigger CPU socket, traces issue can be solved by placing 2 CAMM like slot on back side of PCB where CPU socket is placed, to have shortest route from CPU.

Yes, but that raises the issue is there new motherboards for Zen 6 with the extra memory bandwidth capability of that architecture? As it is now, I'm sure you know B850 & X870 boards do not have CAMM slots on back side of the motherboard with current designs on the market.

 

[rusTORK]

AMD is expected to give "Medusa Point" a new dual memory controller architecture. There are still two DDR5 channels per socket, but this is redesigned for increased memory speeds, letting AMD catch up with Intel in this area.

What dual memory controller architecture mean? Support two diffirent memory types? Which? I remember that AMD said that current 9800X3D don't supprt CKD memory and it can't be added without redisign.

 

[Nhonho]

Why limit yourself? Mobile Ryzen has 12 core CCDs.

Also, please learn what an E core is, and what a ryzen C core is. These are not the same thing.

Here we go again...

Tell us what desktop applications need dozens of cores other than video encoding by the CPU?

 

[Crackong]

Medusa Ridge ?

 

[Oberon]

The big difference won't be just in the memory controller but also the interconnect between the IOD and CCDs. We're going to get the same style interconnect as Strix Halo but clocked MUCH faster.

 

[Punkenjoy]

AMD is expected to give "Medusa Point" a new dual memory controller architecture. There are still two DDR5 channels per socket, but this is redesigned for increased memory speeds, letting AMD catch up with Intel in this area.

What dual memory controller architecture mean? Support two diffirent memory types? Which? I remember that AMD said that current 9800X3D don't supprt CKD memory and it can't be added without redisign.

What it mean in this context is probably instead of having 1 memory controller driving 2 channel (4 in reality since DDR5 use 2x32 bit channel per dimm), you will have 2 different memory controller with their own queues driving a single channel (1 DIMM or 2x32 bit DDR5 per DIMM)

As per the explanation, i suspect this will allow each memory controller to be smaller so the signal will have less area/distance to propagate, allowing higher frequency. This could also help with signal integrity.

The goal would be to support higher DDR5 clock allowing more bandwidth.

 

[Chaitanya]

CUDIMM support and upgraded memory controller for stable opertation at speeds higher than 5200 with all 4 slots filled.

 

[R-T-B]

Tell us what desktop applications need dozens of cores other than video encoding by the CPU?

I can name a few, but none you'd run, I'd wager.

 

[kondamin]

No rdna 3.5 igpu upgrade on that iod nor an npu?
I have a hard time believing this will be all there is to zen 6

 

[freeagent]

I wonder if they chose that name because something turns to stone when the benchmark completes

 

[ymdhis]

Finally, they updated the IOD. This may be the AM5 chip that will be worth switching to.

 

[RootinTootinPootin]

dual memory controllers.

latency hit, depending on the design, and for once AMD, make 8000MT's speed not feel like worse using 6000MT's..lol..

 

[sudothelinuxwizard]

Still no expected release date?

 

[JustBenching]

Cores are back on the menu boys.

Finally Intel AMD is increasing core counts.

Here we go again...

Tell us what desktop applications need dozens of cores other than video encoding by the CPU?

A lot but it doesn't matter, dozens of cores on the desktop mean that the half a dozen core CPU would be cheaper (although this is amd we are talking about, they might as well keep charging you 400$ for 8 cores).