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AMD Sampling Next-Gen Ryzen Desktop "Medusa Ridge," Sees Incremental IPC Upgrade, New cIOD

As long as it stays small in proportion I'll be happy. I'm glad AMD doesn't waste the die space. A 2D blitter is all that's needed for window compositing.
I doubt they would make them cheaper just because they are small and generally useless
 
Making the GPU bigger does increase the price though. That's already been clearly demonstrated with the MAX 300 range, aka Strix Halo. They're basically exactly what you've requested - A full blown chiplet set with a bloated I/O die containing a 8060 class GPU.

As I first stated, those sorts of APU packages will come along later.
 
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I've gathered the dual memory controllers are for "single channel, per controller" operation but, could this lay the foundation for 'not-quad channel' (in the same vein of DDR5's 'not-ECC')?

Basically, I'm thinking:
Each memory controller might not be 'fully loaded' with only 1 DIMM attached, and 2DIMMs per controller provides more bandwidth.
 
Making the GPU bigger does increase the price though. That's already been clearly demonstrated with the MAX 300 range, aka Strix Halo. They're basically exactly what you've requested - A full blown chiplet set with a bloated I/O die containing a 8060 class GPU.

As I first stated, those sorts of APU packages will come along later.
Strix point is a monolithic die that is also wired for gddr, normal ryzen chips have the igpu on the io die which is tiny and just quadrupling the number of CU on that isn’t going to make it all that much bigger
 
As long as it stays small in proportion I'll be happy. In other words, it stays insignificant and not worth any conversation. Leave the GPU beefing up to the APUs.

I've gathered the dual memory controllers are for "single channel, per controller" operation but, could this lay the foundation for 'not-quad channel' (in the same vein of DDR5's 'not-ECC')?

Basically, I'm thinking:
Each memory controller might not be 'fully loaded' with only 1 DIMM attached, and 2DIMMs per controller provides more bandwidth.
It looks like it had always been a single controller, on the AM4/AM5 platforms, that managed multiple channels. To always effect 128-bit wide operation, filling one request at a time.
Zen6 changes that to be two 64-bit wide independent controllers that feeds two requests at a time. Presumably it'll still have the ability to fill single requests at double the rate.
In theory, for AM5 only, the controller count could be doubled again to 4 x 32-bit wide. This would then match the number of physical channels.
 
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Strix point is a monolithic die that is also wired for gddr, normal ryzen chips have the igpu on the io die which is tiny and just quadrupling the number of CU on that isn’t going to make it all that much bigger
Strix Point can not use GDDR. Funnily they probably could add a GDDR7 memory controller if they got rid of the useless NPU which is a literal waste of sand.
 
Strix Point can not use GDDR. Funnily they probably could add a GDDR7 memory controller if they got rid of the useless NPU which is a literal waste of sand.
Could have sworn it used gddr, but yes it’s lpddr5 they surrounded the Soc with like they do a gpu with gddr
 
Could have sworn it used gddr, but yes it’s lpddr5 they surrounded the Soc with like they do a gpu with gddr
That's true, but your post just make me think that a GDDR APU would rock.
 
That's true, but your post just make me think that a GDDR APU would rock.
Sony's and MSFT's Game Consoles, would indicate that they do indeed rock (vs. DDR System Memory sharing).

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The latest rumor. Not just N2, but N2P for desktop, server and high level mobile parts logic chiplets. For Zen 6.
 
Why limit yourself? Mobile Ryzen has 12 core CCDs.

Also, please learn what an E core is, and what a ryzen C core is. These are not the same thing.


CAMM2 modules are having the same signal integrity issues that DIMM modules have trying to push past 6000 mhz.


It'd be a lot easier to simply put a x3d cache on their APUs instead of another memory controller. Not to mention that a triple bus system is going to be significantly more expensive for the end consumer than a dual pus system like we have now.
i dont know of any mobile 12core CCD.
 
i dont know of any mobile 12core CCD.
They probably the 2 CCX on Strix Point. Its wrong but I get how one would make that mistake.
 
Here we go again...

Tell us what desktop applications need dozens of cores other than video encoding by the CPU?

Tell us why Intel thought it was okay to keep us on 4 Core / 8 Thread CPUs when the market screams for more? People don't just use do 1 thing at a time today, I want to game, I want to render, I want to browse, I want a movie in the background and I want to do it all at once without one affecting the other.

Anyways, looking forward to seeing what a Zen 6 12-Core X3D chip can do, 7Ghz with an IPC uplift? Yes please, I was excited for the 9800X3D, but I held off, I knew the upcoming one will be a beast, good things happen in 3. At the same time, I think for the first time, they will probably have to launch a new socket, hopefully not, but likely.
 
Intel had 6 core chips for 379$ since 2014 my man.
Oh really? That means with how much the 9600X costs a 6-core hasn't really dropped in price.
 
The only 6 core that Intel sold in 2014 was the $600 i7 4930K, which would be $800 today. Competition from AMD is a good thing or we'd probably still be stuck on quad cores unless buying a ridiculously expensive HEDT system. CPU's have gotten faster and cheaper.
 
The only 6 core that Intel sold in 2014 was the $600 i7 4930K, which would be $800 today. Competition from AMD is a good thing or we'd probably still be stuck on quad cores unless buying a ridiculously expensive HEDT system. CPU's have gotten faster and cheaper.
JFC man get your facts straight. 5820K. Just three minutes is all it takes for your posts to not be ignorant.


Let’s not forget to Intel shipped the first multicore x86 processor.
 
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They probably the 2 CCX on Strix Point. Its wrong but I get how one would make that mistake.
Those are designed differently, the AI HX chips are on a single monolithic die. 4 zen 5, and 8 zen 5c cores, plus the igpu on a single die.
 
Let’s not forget to Intel shipped the first multicore x86 processor.
When? In same month in the same year with AMD 64 x2 and Intel CPU Pentium D in the name of the true was not multicore, just 2*1 cores glued together.

Ps. AMD Thuban was first 6 core CPU for the consumers. The flagship from first series: Phenom II X6 1090T was with MSRP 295$.
 
Those are designed differently, the AI HX chips are on a single monolithic die. 4 zen 5, and 8 zen 5c cores, plus the igpu on a single die.
Yes, but the Zen 5 is on one CCX and the Zen 5c is on another. Don't confuse CCDs (compute chiplets), and CCX (core complexes of which mulitple can exist on a monolithic die).
 
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