Nikon Introduces 600x600 mm Substrates for Advanced AI Silicon

[AleksandarK]

Nikon announced that it will begin accepting orders today for its Digital Lithography System DSP-100, a back-end tool purpose-built for the next-gen of advanced semiconductor packaging. The company will deliver the first units during fiscal year 2026. The DSP-100 is specifically designed for panel-level packaging (PLP), a technology that industry leaders such as TSMC, Intel, and Samsung are adopting to overcome the cost and area limitations of 300 mm wafers. Standardized rectangular substrates, already fixed at 510x515 mm, allow more compute chiplets, HBM4 stacks, and I/O dies to be integrated into a single package. Nikon's engineers pushed the standard further by enabling exposure on glass or resin panels up to 600×600 mm. Key specifications released today show a 1.0 µm line‑and‑space resolution, overlay accuracy within ± 0.3 µm and throughput of 50 panels per hour at the 510x515 mm size.

By eliminating photomasks and instead steering an i-line equivalent light source through a spatial light modulator (SLM), the DSP-100 sidesteps both the optical distortion inherent in large single-lens systems and the expense of mask sets. A proprietary multi‑lens array borrowed from Nikon's flat‑panel display division stitches the pattern seamlessly across the full substrate. With a 600×600 mm panel accommodating 36 of the 100 mm square packages, the system delivers nine times higher throughput productivity compared to 300 mm wafer processes, dramatically reducing the cost per die. The maskless architecture also shortens design iteration cycles, a critical advantage as generative AI workloads drive rapid evaluation of data center accelerators. Nikon states that volume production of the DSP‑100 will commence in 2026, with pricing disclosed only to qualified buyers.



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[Panther_Seraphin]

This is interesting news as it could really shake up things if the get adopted enough mass.

I know 450mm wafers were planned/experimented with but went no where due to cost issues initially.

Now that silicon demand is going insane this could really improve throughout and lower costs of larger monolithic dies

 

[kondamin]

600cm² of hbm to feed a 750mm² inferencing chip

 

[agent_x007]

So... how they plan to grow unified silicon crystal into rectangle ?
We don't use a round 300mm wafers because we like to - it's because that's how we guarantee uniformity (and lack of defects) across all 300mm of space. Some 10+ years ago there was a push for 450mm wafers which "failed plat on it's face" when cost of implementing it, and increased chances of defects due to size, came into talks (I guess they never figured out how to implement it in mass production since there are no talks about it now).

 

[DutchTraveller]

So... how they plan to grow unified silicon crystal into rectangle ?
We don't use a round 300mm wafers because we like to - it's because that's how we guarantee uniformity (and lack of defects) across all 300mm of space. Some 10+ years ago there was a push for 450mm wafers which "failed plat on it's face" when cost of implementing it, and increased chances of defects due to size, came into talks (I guess they never figured out how to implement it in mass production since there are no talks about it now).

These are not silicon but glass or resin as it says in the article. They are used as a base for the silicon chips to connect many of them.
Similar to what is done in modern multi-chip CPU's but with much larger panels.
The larger the size the more can be processed at once for increased efficiency and lower costs.
Once processed (all the chips and other components are placed they will be cut into parts.