- Joined
- Oct 9, 2007
- Messages
- 47,692 (7.42/day)
- Location
- Dublin, Ireland
| System Name | RBMK-1000 |
|---|---|
| Processor | AMD Ryzen 7 5700G |
| Motherboard | Gigabyte B550 AORUS Elite V2 |
| Cooling | DeepCool Gammax L240 V2 |
| Memory | 2x 16GB DDR4-3200 |
| Video Card(s) | Galax RTX 4070 Ti EX |
| Storage | Samsung 990 1TB |
| Display(s) | BenQ 1440p 60 Hz 27-inch |
| Case | Corsair Carbide 100R |
| Audio Device(s) | ASUS SupremeFX S1220A |
| Power Supply | Cooler Master MWE Gold 650W |
| Mouse | ASUS ROG Strix Impact |
| Keyboard | Gamdias Hermes E2 |
| Software | Windows 11 Pro |
AMD today launched the EPYC Embedded 9005 line of server processors in the embedded form-factor. These are non-socketed variants of the EPYC 9005 "Turin" server processors. The chips are intended for servers and other enterprise applications where processor replacements or upgradability are not a consideration. The EPYC Embedded 9005 "Turin" are otherwise every bit similar to the regular socketed EPYC 9005 series. These chips are based on a BGA version of the "Turin" chiplet-based processor, and powered by the "Zen 5" microarchitecture. Besides the BGA package, the EPYC Embedded 9005 series comes with a few features relevant to its form-factor and target use-cases.
To begin with, the EPYC Embedded 9005 "Turin" series comes with NTB (non-transparent bridging), a technology that enables high-performance data transfer between two processor packages across different memory domains. NTB doesn't use Infinity Fabric or even CXL, but a regular PCI-Express 5.0 x16 connection. It isn't intended to provide cache coherence, but to absorb faults across various memory domains. Next up, the series supports DRAM flush for enhanced power-loss mitigation. Upon detecting a power loss, the processor immediately dumps memory onto NVMe storage, before the machine turns off. On restart, the BIOS copies this memory dump from the NVMe SSD back to DRAM. Thirdly, the processors in the series support dual SPI flash interfaces, which enables system architects to embed lightweight operating systems directly onto a 64 MB SPI flash ROM, besides the primary SPI flash that stores the system BIOS. This lightweight OS can act like a bootloader for operating systems in other local storage devices.
The AMD EPYC Embedded 9005 "Turin" series scales between 8-core to 192-core, with a maximum L3 cache of 512 MB, maximum PCIe Gen 5 lane count of 160, and memory bandwidth of up to 614 GB/s over twelve DDR5 memory channels. The lineup not just includes processor models with "Zen 5" chiplets (up to 8 full-sized Zen 5 cores per CCD), but also models with "Zen 5c" chiplets (up to 16 Zen 5c cores per CCD).
The table below details the specific processor models and their OPNs, along with their CPU core types, core counts, clock speeds, and TDP. The processor models with "Zen 5c" cores generally come in higher core-counts, such as the 128-core EPYC Embedded 9745, the 160-core EPYC Embedded 9845, and the mammoth 192-core EPYC Embedded 9965. The highest core-count with "Zen 5" cores is the 128-core EPYC Embedded 9755.
The complete slide deck follows.
View at TechPowerUp Main Site
To begin with, the EPYC Embedded 9005 "Turin" series comes with NTB (non-transparent bridging), a technology that enables high-performance data transfer between two processor packages across different memory domains. NTB doesn't use Infinity Fabric or even CXL, but a regular PCI-Express 5.0 x16 connection. It isn't intended to provide cache coherence, but to absorb faults across various memory domains. Next up, the series supports DRAM flush for enhanced power-loss mitigation. Upon detecting a power loss, the processor immediately dumps memory onto NVMe storage, before the machine turns off. On restart, the BIOS copies this memory dump from the NVMe SSD back to DRAM. Thirdly, the processors in the series support dual SPI flash interfaces, which enables system architects to embed lightweight operating systems directly onto a 64 MB SPI flash ROM, besides the primary SPI flash that stores the system BIOS. This lightweight OS can act like a bootloader for operating systems in other local storage devices.
The AMD EPYC Embedded 9005 "Turin" series scales between 8-core to 192-core, with a maximum L3 cache of 512 MB, maximum PCIe Gen 5 lane count of 160, and memory bandwidth of up to 614 GB/s over twelve DDR5 memory channels. The lineup not just includes processor models with "Zen 5" chiplets (up to 8 full-sized Zen 5 cores per CCD), but also models with "Zen 5c" chiplets (up to 16 Zen 5c cores per CCD).
The table below details the specific processor models and their OPNs, along with their CPU core types, core counts, clock speeds, and TDP. The processor models with "Zen 5c" cores generally come in higher core-counts, such as the 128-core EPYC Embedded 9745, the 160-core EPYC Embedded 9845, and the mammoth 192-core EPYC Embedded 9965. The highest core-count with "Zen 5" cores is the 128-core EPYC Embedded 9755.
The complete slide deck follows.
View at TechPowerUp Main Site