- Joined
- Jun 30, 2008
- Messages
- 330 (0.06/day)
Hi,
Trying to understand how Pci Express lanes in lets say a 6850k processor are allocated and controlled. As I understand you have four controllers inside the cpu that manage the lane allocation. IOU 0-3 controlling 1 4X, 1 8X, and 2 16X lane pairs. Looking into my bios with Amibcp I have also noticed there are four IIO divisions that control their own set of IOU’s so I’m a little confused about how its all designed if someone could help explain this all?
Thanks
Trying to understand how Pci Express lanes in lets say a 6850k processor are allocated and controlled. As I understand you have four controllers inside the cpu that manage the lane allocation. IOU 0-3 controlling 1 4X, 1 8X, and 2 16X lane pairs. Looking into my bios with Amibcp I have also noticed there are four IIO divisions that control their own set of IOU’s so I’m a little confused about how its all designed if someone could help explain this all?
Thanks