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Intel Corp. said this week that its forthcoming Itanium processor code-named Montecito with two processing engines delivers world's record performance in LINPACK benchmark, which measures floating point speed. The claim should prove the power of dual-core Intel Itanium chip and create rush around Intel's dual-core products.
Using the LINPACK benchmark, a system with four dual-core Itanium processors exceeded 45 GFLOPs (gigaflops), a measure of computer speed where a gigaflop is 1 billion floating-point operations per second. The previous record was 27.5 GFLOP, Intel indicated.
"This performance result gives a peek into the advantage Montecito is expected to have over previous generations of the Itanium architecture for high-performance computing applications," said Phil Brace, general manager of Intel's Server Platform Group. "Three years ago we showed a four-processor Itanium-based system at 11.43GFLOPs, and two years ago we hit 22.7GFLOPs.2 We are approaching the ability to reach a TeraFlop in as few as a 20-server system cluster and helping to dramatically increase the affordability to the scientific community."
Montecito will be Intel's first IA64 chip with two cores and 24MB of L3 cache. In 2003 Intel uncovered plans to implement its special "arbiter" bus into the chip code-named Montecito to manage how the cores collaborate between themselves, how they utilise their processor system bus and the L3 cache. No actual peculiarities of the design have been presented by Intel officials so far, but we can pre-suppose that the "arbiter" bus architecture may be utilised in all multiple-core CPUs from Intel that will come in future.
Intel's Itanium chips with two processing engines are expected to work using 667MHz Quad Pumped Bus and will feature Intel's new core-logic for high-end servers code-named Bayshore. The latter is expected to provide support for DDR2 memory and PCI Express interconnection, bringing the latest innovations into the server market.
The Montecito chip will contain a couple of promising technologies: Foxton for dynamic power management and Pellston for correcting data errors in the cache. Intel's chief executive Paul Otellini said that the Foxton is a technology to dynamically boost speed of Itanium 2 chips, but he did not outline, whether this applies to dynamic overclocking or dynamic underclocking. Typically, overclocking is not accepted in mission-critical environments, at the same time, dynamic underclocking can help to reduce power consumption and consequently the cost of ownership.
Intel demonstrated a 4-way demo system based on dual-core Montecito processors in August, 2004, which proved capable of running up to 16 applications at a time due to the fact that each of the Montecito cores supports Hyper-Threading technology. As an example of the practical application of a computer like that Intel showed a weather simulator program from NASA and added that with all this potential a computer like that appears 50% faster than the fastest super-computer on the planet then, offering the performance of 60TFlops using equal amount of processors.
While boosting performance, Montecito is expected to also deliver more than 20% lower power than previous generations of Itanium processors through new technologies for power management.
Source : X-bit labs
View at TechPowerUp Main Site
Using the LINPACK benchmark, a system with four dual-core Itanium processors exceeded 45 GFLOPs (gigaflops), a measure of computer speed where a gigaflop is 1 billion floating-point operations per second. The previous record was 27.5 GFLOP, Intel indicated.
"This performance result gives a peek into the advantage Montecito is expected to have over previous generations of the Itanium architecture for high-performance computing applications," said Phil Brace, general manager of Intel's Server Platform Group. "Three years ago we showed a four-processor Itanium-based system at 11.43GFLOPs, and two years ago we hit 22.7GFLOPs.2 We are approaching the ability to reach a TeraFlop in as few as a 20-server system cluster and helping to dramatically increase the affordability to the scientific community."
Montecito will be Intel's first IA64 chip with two cores and 24MB of L3 cache. In 2003 Intel uncovered plans to implement its special "arbiter" bus into the chip code-named Montecito to manage how the cores collaborate between themselves, how they utilise their processor system bus and the L3 cache. No actual peculiarities of the design have been presented by Intel officials so far, but we can pre-suppose that the "arbiter" bus architecture may be utilised in all multiple-core CPUs from Intel that will come in future.
Intel's Itanium chips with two processing engines are expected to work using 667MHz Quad Pumped Bus and will feature Intel's new core-logic for high-end servers code-named Bayshore. The latter is expected to provide support for DDR2 memory and PCI Express interconnection, bringing the latest innovations into the server market.
The Montecito chip will contain a couple of promising technologies: Foxton for dynamic power management and Pellston for correcting data errors in the cache. Intel's chief executive Paul Otellini said that the Foxton is a technology to dynamically boost speed of Itanium 2 chips, but he did not outline, whether this applies to dynamic overclocking or dynamic underclocking. Typically, overclocking is not accepted in mission-critical environments, at the same time, dynamic underclocking can help to reduce power consumption and consequently the cost of ownership.
Intel demonstrated a 4-way demo system based on dual-core Montecito processors in August, 2004, which proved capable of running up to 16 applications at a time due to the fact that each of the Montecito cores supports Hyper-Threading technology. As an example of the practical application of a computer like that Intel showed a weather simulator program from NASA and added that with all this potential a computer like that appears 50% faster than the fastest super-computer on the planet then, offering the performance of 60TFlops using equal amount of processors.
While boosting performance, Montecito is expected to also deliver more than 20% lower power than previous generations of Itanium processors through new technologies for power management.
Source : X-bit labs
View at TechPowerUp Main Site