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Intel is designing a "Halo" SKU of a future generation of mobile processors with a goal to match Apple's in-house silicon of the time. Slated for tape-out some time in 2023, with mass-production expected in 2024, the 15th Generation Core "Arrow Lake-P Halo" processor is being designed specifically to compete with Apple's "premium 14-inch laptop" (presumably the MacBook Pro) that the company could have around 2024, based on an in-house Apple silicon. This is to essentially tell its notebook partners that they will have an SoC capable of making their devices in the class truly competitive. Apple relies on a highly scaled out Arm-based SoC based on in-house IP blocks, with a software that's closely optimized for it. Intel's effort appears to chase down its performance and efficiency.
The Core "Arrow Lake" microarchitecture succeeds the 14th Gen "Meteor Lake." It is a multi-chip module (MCM) of three distinct dies built on different fabrication nodes, in line with the company's IDM 2.0 strategy. These nodes are Intel 4 (comparable to TSMC N7 or N6), Intel 20A (comparable to TSMC N5), and an "external" 3 nm-class node that's just the TSMC N3. The compute tile, or the die which houses the CPU cores, combines a hybrid CPU setup of 6 P-cores, and 8 E-cores. The performance cores are likely successors of the "Redwood Cove" P-cores powering the "Meteor Lake" compute tiles. Intel appears to be using one kind of E-cores across two generations (eg: Gracemont across Alder Lake and Raptor Lake). If this is any indication, Arrow Lake could continue to use "Crestmont" E-cores. Things get interesting with the Graphics tile.
With Meteor Lake, Intel is disaggregating the iGPU out of both the "processor die" and the platform tile. The company understands the importance of having a fast iGPU in the wake of competition from not just Apple, but also AMD tapping into its latest RDNA-series IP to create powerful iGPUs. The graphics tile of Arrow Lake-P Halo will very likely be based on the node with the highest transistor density (our money is on TSMC N3). This tile features a whopping 320 execution units (EUs), which work out to 2,560 unified shaders. Intel is designating the iGPU its highest performance designation in the series, "GT3." The least advanced node of the three, Intel 4, could be used for the platform or I/O tiles, which house the memory controllers, PCIe root-complexes, and various SoC I/O interfaces.
View at TechPowerUp Main Site | Source
The Core "Arrow Lake" microarchitecture succeeds the 14th Gen "Meteor Lake." It is a multi-chip module (MCM) of three distinct dies built on different fabrication nodes, in line with the company's IDM 2.0 strategy. These nodes are Intel 4 (comparable to TSMC N7 or N6), Intel 20A (comparable to TSMC N5), and an "external" 3 nm-class node that's just the TSMC N3. The compute tile, or the die which houses the CPU cores, combines a hybrid CPU setup of 6 P-cores, and 8 E-cores. The performance cores are likely successors of the "Redwood Cove" P-cores powering the "Meteor Lake" compute tiles. Intel appears to be using one kind of E-cores across two generations (eg: Gracemont across Alder Lake and Raptor Lake). If this is any indication, Arrow Lake could continue to use "Crestmont" E-cores. Things get interesting with the Graphics tile.
With Meteor Lake, Intel is disaggregating the iGPU out of both the "processor die" and the platform tile. The company understands the importance of having a fast iGPU in the wake of competition from not just Apple, but also AMD tapping into its latest RDNA-series IP to create powerful iGPUs. The graphics tile of Arrow Lake-P Halo will very likely be based on the node with the highest transistor density (our money is on TSMC N3). This tile features a whopping 320 execution units (EUs), which work out to 2,560 unified shaders. Intel is designating the iGPU its highest performance designation in the series, "GT3." The least advanced node of the three, Intel 4, could be used for the platform or I/O tiles, which house the memory controllers, PCIe root-complexes, and various SoC I/O interfaces.
View at TechPowerUp Main Site | Source
