Intel to Introduce Native 2MB L2 Cache Conroe

[malware]

In order to lower the Allendale production costs, Intel will release native 2MB L2 Conroe in February 2007. Similarly, Merom will also get native 2MB L2 cache version at the time of Santa Rosa release. The existing Intel Core 2 Duo and Xeon 3000 are actually native 4MB L2 processors. Although they have 2MB L2 and 4MB L2 versions, Allendales(2MB L2) are made by only disabling half of the L2 Cache. CPUs to have native 2MB L2 include Core 2 Duo E6300 (1.86GHz), E6400 (2.13GHz), Xeon 3040 (1.86GHz) and Xeon 3050 (2.13GHz). Their steppping will be changed from B2 to L2m, as well as the CPUID from 6F6 to 6F2. Only a BIOS update will be needed to recognize the CPUs properly, when they come.

View at TechPowerUp Main Site

 

[Slater]

Soooo somehow it is possible to regain those 2mb's that are disabled.

 

[malware]

Soooo somehow it is possible to regain those 2mb's that are disabled.

Don't count on it.

 

[Slater]

Theoretically it is possible though.

 

[jocksteeluk]

why on earth disable something that is already on the chip? how can that be cheaper than not putting the extra 2mb on the chip instead?

 

[Slater]

Well considering you would need an entire new manufacturing process for that....

 

[jocksteeluk]

why would they need an entire new process to add a 2mb cache chip instead of a 4mb cahe chip unless i am mistaken and the memory is built onto the die itsself?

 

[Dippyskoodlez]

Theoretically it is possible though.

No, theoretically it is not possible. Much like the A64, Intel too has been using in die cpu fuses and ops to disable things.

If you wanna kill yours with a pin mod attempt, be my guest.

why on earth disable something that is already on the chip? how can that be cheaper than not putting the extra 2mb on the chip instead?

It reduces die size dramaticaly. Cache @ 4mb is probably well over half the die on the C2d's.

Well considering you would need an entire new manufacturing process for that....

You only need to re cast the cpu die, not excactly uncommon for intel. Much worth it with a change this big.

Seems like Intel's prepping for K8L awefully early this time. Stripping 2MB to help ramping perhaps?

 

[jocksteeluk]

cheers for that

 

[Alec§taar]

It reduces die size dramaticaly. Cache @ 4mb is probably well over half the die on the C2d's.

Yea, that'd work, IF they never put it there in the first place!

HOWEVER, from what I read above & what * I THINK * that jocksteeluk's asking is, is this:

"Why DISABLE something that's on the chip in the first place @ all, since the monies & materials were spent adding it onto it in the FIRST place?"

* After all: The added L2 cache, disabled or not, still uses the same amt. of material for that onboard L2 cache memory... & is a waste of materials @ the very least putting it there & just 'disabling' it.

APK

P.S.=> Since they're ALL from the same production run? Instead of starting another one, that actually DOES put less L2 cache memory onto the CPU?? I can see them doing this... especially IF the added L2 cache (or portions of it) aren't working "up to spec".

From what I understand @ least about CPU manufacture? Is that when certain CPU's from a sample (that lot # off the production line) don't "make it" as far as say, the lot# before it, for something like GHZ speed ratings?? They label them as less than what their potential is... & maybe disable some things on the CPU die itself...

This case isn't the same as THAT, though... @ least I don't think so! apk

 

[Polaris573]

"Why DISABLE something that's on the chip in the first place @ all, since the monies & materials were spent adding it onto it in the FIRST place?"

Greed.

 

[newtekie1]

why on earth disable something that is already on the chip? how can that be cheaper than not putting the extra 2mb on the chip instead?

Cut down on production costs, they have to do something with those chips that don't pass the L2 Cache test after being made. It is either throw them out, or disable half and sell them as lower processors. You can also bet they have some with 1MB or maybe even 512MB L2 Cache that they are stocking up on in anticipation of the Conroe based Celerons.

 

[Saurian]

Shrink the die (remove 2MB of cache), and you get more processors from each wafer in production, lowers cost. As said, current E6300's/E6400's are processors that could not pass L2 cache requirements.

I wonder if you're right, newtekie. Something I'm curious about, as well.

 

[tvdang7]

well since the current allendales overclock well already ,how will the new ones do ,do u think?

 

[Dippyskoodlez]

well since the current allendales overclock well already ,how will the new ones do ,do u think?

Probably very similar. Its not a change that would effect clockspeeds nearly as much since the old ones are only running 2mb already.

If anything it loses surface area of the die, so if the temperature difference is big enough (which I doubt) it would/could be worse.

But if intel adds silicon tweaks, its comparing apples to oranges then.