SK hynix Develops MCR DIMM, World's Fastest Server Memory Module

[btarunr]

SK hynix Inc. announced today that it has developed working samples of DDR5 Multiplexer Combined Ranks (MCR) Dual In-line Memory Module, the world's fastest server DRAM product. The new product has been confirmed to operate at the data rate of minimum 8 Gbps, and at least 80% faster than 4.8 Gbps of the existing DDR5 products. MCR DIMM is an achievement coming from out-of-the-box thinking with an aim to improve the operation speed of DDR5. Challenging the prevailing concept that the operation speed of DDR5 relies on that of DRAM chip itself, engineers sought to find a way to improve the speed of modules instead of chips for development of the latest product.

SK hynix designed the product in a way that enables simultaneous operation of two ranks by utilizing the data buffer installed onto the MCR DIMM based on Intel's MCR technology. By enabling simultaneous operation of two ranks, MCR DIMM allows transmission of 128 bytes of data to CPU at once, compared with 64 bytes fetched generally in conventional DRAM module. An increase in the amount of data sent to the CPU each time supports the data transfer rate of minimum 8 Gbps, twice as fast as a single DRAM.



A close collaboration with business partners Intel and Renesas was key to success. The three companies worked together and cooperated throughout the process from the product design to verification.

SK hynix's Head of DRAM Product Planning Sungsoo Ryu said that the achievement was possible thanks to convergence of different technologies. "SK hynix's DRAM module-designing capabilities were met with Intel's excellence in Xeon processor and Renesas' buffer technology," Ryu said. "For a stable performance of MCR DIMM, smooth interactions between the data buffer and processor in and out of the module are essential."

Data buffer transmits multiple signals coming from the module in the middle and server CPU accepts and handles the signals coming though the buffer.

"SK hynix delivered another technological evolution for DDR5 by developing the world's fastest MCR DIMM," Ryu said. "Our efforts to find technological breakthroughs will continue as we seek to solidify our leadership in the server DRAM market."

Dr. Dimitrios Ziakas, Vice President of Memory and IO Technologies at Intel, said that Intel and SK hynix are leading the way on memory innovation and the development of high performance, scalable DDR5 for servers, along with other key industry partners.

"The technology brought forward comes from years of collaborative research between Intel and key industry partners to produce significant increases in deliverable bandwidth for Intel Xeon processors," he said. "We look forward to bringing this technology to future Intel Xeon processors and supporting standardization and multigenerational development efforts across the industry."

Vice President and General Manager of Memory Interface Division at Renesas Sameer Kuppahalli said that Renesas' development of the data buffer is a culmination of three years of intensive effort spanning from concept to productization. "We're proud to partner with SK hynix and Intel in the endeavor to realize this technology into a compelling product," he said.

SK hynix expects the market for the MCR DIMM to expand driven by high performance computing that will take advantage of the increased memory bandwidth. SK hynix is planning to bring the product to mass production in the future.

View at TechPowerUp Main Site

 

[wEeViLz]

sounds expensive

 

[marios15]

Classic DDR upgrade cycle

for (n = 0; n < n+1; n++)
{
Release DDR(n+1) garbage chips with speeds barely faster than DDR(n)
Sell DDR(n+1) chips for prices 2-10x higher than DDR(n)
Announce "breakthrough" for 2-3x faster DDR(n+1) frequencies than DDR(n) when RAM prices begin dropping
}

Since 2000

 

[Wirko]

This is DDR6 basically. A bit oversimplified but every generation doubles the parallelism to extract double the data rate from the same old and slow DRAM memory cells.

 

[Minus Infinity]

This is DDR6 basically. A bit oversimplified but every generation doubles the parallelism to extract double the data rate from the same old and slow DRAM memory cells.

That would mean basic garbage level DDR6 would be 9600MT's.

As for DDR5 give us lower latencies. CL 26 @ 6000 rather than CL38 @ 8000

 

[trsttte]

That would mean basic garbage level DDR6 would be 9600MT's.

As for DDR5 give us lower latencies. CL 26 @ 6000 rather than CL38 @ 8000

That would be like CL13 3000MT DDR4, won't happen anytime soon. CL38 at 8000 has the same latency as CL19 at 4000 on ddr4, not great but very respectable