X3D/vertically stacked cache - ignored or only achievable now?

[wheresmycar]

I'm just info-probing as usual to kill the curiousity

Going off w1zzard's recently added 53-game 5800X v 5800X3D benchmark (below) which sees some pretty amazing X3D performance gains in a number of titles.... i'm just wandering why this V-cache implemention has only recently materialized - 6 months ago. Is this something which wasn't possible previously? Maybe overlooked or was it down to architectural/component make-up limitations or were games not as cache demanding previously.... or a mix bag/other intolerables? Also why hasn't Intel caught on... or is this something in the plan and execute pipeline? I'm just surprised this sort of performance uplift is a recent phenomena and seeing AM5 its being treated as an on-going one-trick pony per Gen. Seems like we're going to continue seeing Intel/AMD fighting for the ST/MT performance crown for the baseline offerings with X3D parts being a secondary delicacy, perhaps one at a rediculous asking price at launch.

.....basically v-cache inquisitive and annoyed with AMD not having kick started AM5 with X3D from the get-go!

 

[cvaldes]

While I have zero evidence, my guess is that prototypes of various technologies have been running in these companies' labs for years (AMD, Intel, NVIDIA, Apple, etc.). In the same way, there are probably CPUs with differentiated silicon (performance cores + efficiency cores) in AMD's labs. Apple probably had them running for years before they shipped in their A-series SoCs (Apple A10, released 2016).

Why hasn't Intel released CPUs with V-cache? Only they know for sure. It's likely that it's a combination of factors (not just one) that doesn't make it feasible at this time.

Remember that something like V-cache isn't free. There's a cost to it whether it be manufacturing difficulty or transistors (i.e., more L3 cache). Intel's on a much bigger process node which might affect the feasibility of this particular feature. AMD has moved to chiplets whereas Intel is still hanging onto the monolithic die.

People here who know more about processor technology will likely be able to clarify the matter but ultimately it's all a matter of conjecture because Intel won't disclose why they haven't commercialized this technology in shipping product.

But I guarantee you that some very, very smart Intel engineers have examined AMD 5800X3D parts very carefully. And what they think about it is going to stay on Intel's campus, company confidential e-mails, and internal chat rooms.

 

[oxrufiioxo]

My guess is greed being the main reason we are not seeing 3D vcache varients at launch. I'm pretty confident AMD didn't expect Raptorlake to be so competitive especially after Alderlake with it's superior ST performance didn't really catch on vs Ryzen 5000. With Ryzen 7000 seemingly doing poorly most likely due to motherboard/memory cost and strong competition from Raptorlake we likely will see 3D varients sooner rather than later.

Intel has increased cache quite a bit over the last couple generations I'm guessing it most likely comes down to manufacturing cost as to why they haven't gone the 3D route. Meteorlake seems interesting with it's tiled based approach maybe we will see somthing similar with it.

 

[The red spirit]

I still think that it won't last very long, because Zen 1 with chiplets already had energy density issues and heat transfer from cores to heatsink issues. If you plop some cache on all that, things get worse and you need to limit maximum clocks to deal with heat, which means less performance in non cache size limited workloads. BTW AMD wasn't even the first to experiment with cache in such ways. Intel's Broadwell did it earlier and I'm sure that some enterprise chips already did that a decade if not decades earlier than Broadwell. Seriously, if AMD really thinks that this big cache is going to last, they better start engineering micropore or whatever it was called CPU cooling, where tiny heatpipes are integrated into CPU die. I heard this idea in Pentium 4 era, so it probably wasn't as great as Pentium 4 itself was. With that cooling or some other similarly effective cooling idea, it might be sustainable, but as it is, it definitely isn't sustainable at all. Hell, even 5800X3D already trades clock speed for bigger cache and that's not great. I might be wrong, but isn't cache also more sensitive to heat than CPU itself due to data integrity problems at higher temperatures?

 

[tabascosauz]

I'm just info-probing as usual to kill the curiousity

Going off w1zzard's recently added 53-game 5800X v 5800X3D benchmark (below) which sees some pretty amazing X3D performance gains in a number of titles.... i'm just wandering why this V-cache implemention has only recently materialized - 6 months ago. Is this something which wasn't possible previously? Maybe overlooked or was it down to architectural/component make-up limitations or were games not as cache demanding previously.... or a mix bag/other intolerables? Also why hasn't Intel caught on... or is this something in the plan and execute pipeline? I'm just surprised this sort of performance uplift is a recent phenomena and seeing AM5 its being treated as an on-going one-trick pony per Gen. Seems like we're going to continue seeing Intel/AMD fighting for the ST/MT performance crown for the baseline offerings with X3D parts being a secondary delicacy, perhaps one at a rediculous asking price at launch.

.....basically v-cache inquisitive and annoyed with AMD not having kick started AM5 with X3D from the get-go!

AMD is completely reliant on what TSMC can offer.

TSMC only publicly announced the relevant 3D stacking tech like, mid 2021? SoIC is what AMD is using for 3D V-cache, and is the new stuff.

• 3D Vcache stacks like process on like process (N7-on-N7 for 5800X3D). AMD had to wait for TSMC to approve N5-on-N5 stacking for Ryzen 7000X3D (a N5 product) - TSMC said late 2022 for N5-on-N5
• 5800X3D lost all official OC support and locked to 1.35V (really 1.25V) due to concern over Vcache longevity. If AMD wants to make a X3D product that doesn't sacrifice clocks, then they need to find a way to decouple L3 clock from CPU clock, and L3 voltage from VDDCR_CPU. AM4 doesn't do this, and I'm not sure if AM5 has introduced this yet.
• With current V-cache, thermals are comparatively terrible because of the extra material needed. As Ryzen 7000 V-F stands now, I doubt anything above 5.2GHz is thermally feasible in a X3D product - N7 Ryzen V-F only really improved starting mid-2020, even though it launched fall 2019. Stands to reason that AMD would wait until a few months into N5 for X3D. If V-F improves, X3D is more competitive

Intel has a different approach to stacking, they use bumps for Foveros. AMD uses TSVs for Vcache. Each is better suited only to their own products. Cache itself is relatively simple, compute on compute stacking (ie. Lakefield) is a different matter


edit: N5-on-N5 was delayed to 2023

 

[londiste]

Some rambling thoughts.

x86 architectures have reached the point where there are no low-hanging fruit any more. They cannot get a big performance jump without major changes, more cores are of limited usefulness (when talking about desktop particularly), extending architectural elements has its own downsides - if nothing else then a lot of stuff would have to be re-optimized (as an example, look at M1). So, they go for incremental changes to squeeze every last ounce of performance out of it.

On one hand - V-cache die is about half of the size of CCD. Leaving chiplets aside for a moment this is quite a steep area cost and in the past this was much better spent on other things - more pipes/execution units, more cores, more (lower-level) cache etc. Maybe the simplest example would be that on the same area you could have 12 cores instead of 8. The extra area could also be spent indirectly on things other than architecture. Although all manufacturers do lower-density process variations for high-performance chips Intel has been perhaps most known for tweaking their production nodes (say, 14nm) for maximum frequency.

On the other hand, packaging has been advancing rapidly triggered by relative slowing of manufacturing processes development. 7nm, 5nm and every upcoming one are going to have more technical challenges, going to be more expensive, yields are getting worse. So, new chips are going to be smaller and more expensive. Chiplets have been the talk for a long while now for various applications but the problem has been with getting them connected. Hello TSVs, micro-bumps, interposers (for a while now silicon interposers and optimization methods like EMIB) and this entire area is evolving rapidly. Also new more generalized interconnect architectures like IF or NVLink. Why not earlier? Primarily cost. every advanced packaging trick is more expensive compared to just putting a die on substrate. Not even considering the R&D involved.

V-Cache is sometimes immensely useful and other times not as much. Also, due to vertical stacking 5800X3D seems to have some limitations on voltage and temperature. These problems are likely only going to get worse with more complex Legos for CPUs - or GPUs or APUs or SoCs etc. Most upcoming designs seem to try and avoid vertical stacking for power and temperature consideration.