Monday, December 11th 2017
Rambus Talks HBM3, DDR5 in Investor Meeting
Rambus, a company that has veered around the line of being an innovative company and a patent troll, has shed some more light on what can be expected from HBM3 memory (when it's finally available). In an investor meeting, representatives from the company shared details regarding HBM3's improvements over HBM2. Details are still scarce, but at least we know Rambus' expectations for the technology: double the memory bandwidth per stack when compared to HBM2 (4000 MB/s), and a more complex design, which leaves behind the 2.5D design due to increased height of the HBM3 memory stacks. An interesting thing to note is that Rambus is counting on HBM3 to be produced on 7 nm technologies. Considering the overall semiconductor manufacturing calendar for the 7 nm process, this should place HBM3 production in 2019, at the earliest.
HBM3 is also expected to bring much lower power consumption compared to HBM2, besides increasing memory density and bandwidth. However, the "complex design architectures" in the Rambus slides should give readers pause. HBM2 production has had some apparent troubles in reaching demand levels, with suspected lower yields than expected being the most likely culprit. Knowing the trouble AMD has had in successful packaging of HBM2 memory with the silicon interposer and its own GPUs, an even more complex implementation of HBM memory in HBM3 could likely signal some more troubles in that area - maybe not just for AMD, but for any other takers of the technology. Here's hoping AMD's woes were due only to one-off snags on their packaging partners' side, and doesn't spell trouble for HBM's implementation itself.Other details that surfaced in the Rambus investor meeting pertain to DDR5 memory. Rambus says these will also be built under the 7 nm fabrication process, which is reinforced by Micron's assertions that the new memory specifications would be ready for production in 2020. With higher volume being needed for DDR5 production than HBM3, it makes sense that the latter would see production and sale to customers slightly before DDR5, to test the new 7 nm fabrication processes in a lower volume, higher margin product, ensuring yields of DDR5 to be within adequate rates.
HBM3 is also expected to bring much lower power consumption compared to HBM2, besides increasing memory density and bandwidth. However, the "complex design architectures" in the Rambus slides should give readers pause. HBM2 production has had some apparent troubles in reaching demand levels, with suspected lower yields than expected being the most likely culprit. Knowing the trouble AMD has had in successful packaging of HBM2 memory with the silicon interposer and its own GPUs, an even more complex implementation of HBM memory in HBM3 could likely signal some more troubles in that area - maybe not just for AMD, but for any other takers of the technology. Here's hoping AMD's woes were due only to one-off snags on their packaging partners' side, and doesn't spell trouble for HBM's implementation itself.Other details that surfaced in the Rambus investor meeting pertain to DDR5 memory. Rambus says these will also be built under the 7 nm fabrication process, which is reinforced by Micron's assertions that the new memory specifications would be ready for production in 2020. With higher volume being needed for DDR5 production than HBM3, it makes sense that the latter would see production and sale to customers slightly before DDR5, to test the new 7 nm fabrication processes in a lower volume, higher margin product, ensuring yields of DDR5 to be within adequate rates.