Thursday, March 7th 2019
Toshiba and Western Digital Readying 128-layer 3D NAND Flash
Toshiba and its strategic ally Western Digital are readying a high-density 128-layer 3D NAND flash memory. In Toshiba's nomenclature, the chip will be named BiCS-5. Interestingly, despite the spatial density, the chip will implement TLC (3 bits per cell), and not the newer QLC (4 bits per cell). This is probably because NAND flash makers are still spooked about the low yields of QLC chips. Regardless, the chip has a data density of 512 Gb. With 33% more capacity than 96-layer chips, the new 128-layer chips could hit commercial production in 2020-21.
The BiCS-5 chip reportedly features a 4-plane design. Its die is divided into four sections, or planes, which can each be independently accessed; as opposed to BiCS-4 chips that use a 2-plane layout. This reportedly doubles the write performance per unit-channel to 132 MB/s from 66 MB/s. The die also reportedly uses CuA (circuitry under array), a design innovation in which logic circuitry is located in the bottom-most "layer," with data layers stacked above, resulting in 15 percent die-size savings. Aaron Rakers, a high-technology industry market analyst with Wells Fargo, estimates that Toshiba-WD's yields per 300 mm wafer could be as high as 85 percent.
The BiCS-5 chip reportedly features a 4-plane design. Its die is divided into four sections, or planes, which can each be independently accessed; as opposed to BiCS-4 chips that use a 2-plane layout. This reportedly doubles the write performance per unit-channel to 132 MB/s from 66 MB/s. The die also reportedly uses CuA (circuitry under array), a design innovation in which logic circuitry is located in the bottom-most "layer," with data layers stacked above, resulting in 15 percent die-size savings. Aaron Rakers, a high-technology industry market analyst with Wells Fargo, estimates that Toshiba-WD's yields per 300 mm wafer could be as high as 85 percent.