Tuesday, August 18th 2020
Microsoft Details Xbox Series X SoC, Drops More Details on RDNA2 Architecture and Zen 2 CPU Enhancements
Microsoft in its Hot Chips 32 presentation detailed the SoC at the heart of the upcoming Xbox Series X entertainment system. The chip mostly uses AMD IP blocks, and is built on TSMC N7e (enhanced 7 nm) process. It is a 360.4 mm² die with a transistor count of 15.3 billion. Microsoft spoke about the nuts and bolts of the SoC, including its largest component - the GPU based on AMD's new RDNA2 graphics architecture. The GPU takes up much of the chip's die area, and has a raw SIMD throughput of 12 TFLOP/s. It meets DirectX 12 Ultimate logo requirements, supporting hardware-accelerated ray-tracing.
The RDNA2 GPU powering the Xbox Series X SoC features 52 compute units spread across 26 RDNA2 dual compute units. The silicon itself physically features two additional dual CUs (taking the total physical CU count to 56), but are disabled (possibly harvesting headroom). We've detailed first-generation RDNA architecture in the "architecture" pages of our first AMD Radeon RX 5000-series "Navi" graphics card reviews, which explains much of the SIMD-level innovations from AMD that help it drive a massive SIMD IPC gain over the previous-generation GCN architecture. This hierarchy is largely carried over to RDNA2, but with the addition of a few SIMD-level components.The RDNA2 SIMD (dual compute unit), as detailed by Microsoft in its Xbox Series X SoC presentation, appears similar to that of the original RDNA, with four SIMD32 ALU clusters sharing instruction- and scalar caches. A major difference here is the addition of Intersection Engine components on a per-CU basis (two per dual CU), which Microsoft labels out as "ray-tracing accelerators." The Intersection Engine is a component that's functionally similar to the RT cores found in NVIDIA "Turing" GPUs - its job is to calculate the point of intersection between a ray and a triangle, which makes up BVH - a vital component of hardware ray-tracing. Each RDNA2 dual CU features a total of 128 stream processors.As implemented on the Microsoft SoC, the RDNA2 GPU features a unified geometry engine, hardware support for Mesh Shaders (the other major component of D3D12 Ultimate feature set), a multi-core command processor, multiple Prim and Raster units, and screen tiled color/depth unit. The GPU features a dedicated 3-level cache hierarchy, with L0 caches, shared L1 cache per shader engine, and a shared 5 MB L3 cache.Besides ray-tracing and mesh shaders, the GPU supports the two other components that make up the D3D12U feature-set, including Variable Rate Shading (VRS), and Sampler Feedback Streaming, and an Xbox-exclusive Custom Residency Map Filtering. The Display- and Media-controllers are significantly modernized over the previous-generation Xbox One, with support for HDMI 2.0b, and hardware decode for modern media formats.
As for the CPU, as is already known, the Xbox Series X SoC features 8 CPU cores based on the AMD "Zen 2" microarchitecture. It turns out, that these cores are spread across two CCXs that largely resemble those on AMD's "Renoir" APU, configured with 4 MB of shared L3 cache per CCX. With SMT off, these cores run at a frequency of up to 3.80 GHz, and up to 3.60 GHz with SMT on. The CPU core ISA is largely identical to that of the "Zen 2" cores on AMD Ryzen processors, with the addition of the SPLEAP extension (security privilege level execution and attack protection), which works to prevent privilege escalation attacks. This is a Microsoft-developed hardware component that was present in the "Jaguar" cores that powered the Xbox One SoC, but were ported to "Zen 2." The SoC uses a 320-bit GDDR6 memory interface, with partitioned GDDR6 being used both as video memory and system memory.
The RDNA2 GPU powering the Xbox Series X SoC features 52 compute units spread across 26 RDNA2 dual compute units. The silicon itself physically features two additional dual CUs (taking the total physical CU count to 56), but are disabled (possibly harvesting headroom). We've detailed first-generation RDNA architecture in the "architecture" pages of our first AMD Radeon RX 5000-series "Navi" graphics card reviews, which explains much of the SIMD-level innovations from AMD that help it drive a massive SIMD IPC gain over the previous-generation GCN architecture. This hierarchy is largely carried over to RDNA2, but with the addition of a few SIMD-level components.The RDNA2 SIMD (dual compute unit), as detailed by Microsoft in its Xbox Series X SoC presentation, appears similar to that of the original RDNA, with four SIMD32 ALU clusters sharing instruction- and scalar caches. A major difference here is the addition of Intersection Engine components on a per-CU basis (two per dual CU), which Microsoft labels out as "ray-tracing accelerators." The Intersection Engine is a component that's functionally similar to the RT cores found in NVIDIA "Turing" GPUs - its job is to calculate the point of intersection between a ray and a triangle, which makes up BVH - a vital component of hardware ray-tracing. Each RDNA2 dual CU features a total of 128 stream processors.As implemented on the Microsoft SoC, the RDNA2 GPU features a unified geometry engine, hardware support for Mesh Shaders (the other major component of D3D12 Ultimate feature set), a multi-core command processor, multiple Prim and Raster units, and screen tiled color/depth unit. The GPU features a dedicated 3-level cache hierarchy, with L0 caches, shared L1 cache per shader engine, and a shared 5 MB L3 cache.Besides ray-tracing and mesh shaders, the GPU supports the two other components that make up the D3D12U feature-set, including Variable Rate Shading (VRS), and Sampler Feedback Streaming, and an Xbox-exclusive Custom Residency Map Filtering. The Display- and Media-controllers are significantly modernized over the previous-generation Xbox One, with support for HDMI 2.0b, and hardware decode for modern media formats.
As for the CPU, as is already known, the Xbox Series X SoC features 8 CPU cores based on the AMD "Zen 2" microarchitecture. It turns out, that these cores are spread across two CCXs that largely resemble those on AMD's "Renoir" APU, configured with 4 MB of shared L3 cache per CCX. With SMT off, these cores run at a frequency of up to 3.80 GHz, and up to 3.60 GHz with SMT on. The CPU core ISA is largely identical to that of the "Zen 2" cores on AMD Ryzen processors, with the addition of the SPLEAP extension (security privilege level execution and attack protection), which works to prevent privilege escalation attacks. This is a Microsoft-developed hardware component that was present in the "Jaguar" cores that powered the Xbox One SoC, but were ported to "Zen 2." The SoC uses a 320-bit GDDR6 memory interface, with partitioned GDDR6 being used both as video memory and system memory.