Thursday, August 27th 2020
Intel Whitley Platform for Xeon "Ice Lake-SP" Processors Pictured
Here's is the first schematic of Intel's upcoming "Whitley" enterprise platform for the upcoming Xeon Scalable "Ice Lake-SP" processors, courtesy momomo_us. The platform sees the introduction of the new LGA4189 socket necessitated by Intel increasing the memory channels per socket to 8, compared to 6 of the current-gen "Cascade Lake-SP." The new platform also sees the introduction of PCI-Express gen 4.0 bus, with each socket putting out up to 64 PCI-Express gen 4.0 CPU-attached lanes. This are typically wired out as three x16 slots, two x8 slots, an x4 chipset bus, and a CPU-attached 10 GbE controller.
The processor supports up to 8 memory channels running at DDR4-3200 with ECC. The other key component of the platform is the Intel C621A PCH. The C621A talks to the "Ice Lake-SP" processor over a PCI-Express 3.0 x4 link, and appears to retain gen 3.0 fabric from the older generation C621. momomo_us also revealed that the 10 nm "Ice Lake-SP" processor could have TDP of up to 270 W.
The processor supports up to 8 memory channels running at DDR4-3200 with ECC. The other key component of the platform is the Intel C621A PCH. The C621A talks to the "Ice Lake-SP" processor over a PCI-Express 3.0 x4 link, and appears to retain gen 3.0 fabric from the older generation C621. momomo_us also revealed that the 10 nm "Ice Lake-SP" processor could have TDP of up to 270 W.