Monday, October 2nd 2023
More AMD "Strix Point" Mobile Processor Details Emerge
"Strix Point" is the codename for AMD's next-generation mobile processor succeeding the current Ryzen 7040 series "Phoenix." More details of the processor emerged thanks to "All The Watts!!" on Twitter. The CPU of "Strix Point" will be heterogenous, in that it will feature two different kinds of CPU cores, but with essentially the same ISA and IPC. It is rumored that the processor will feature 4 "Zen 5" CPU cores, and 8 "Zen 5c" cores.
Both core types feature an identical IPC, but the "Zen 5" cores can hold onto higher boost frequencies, and have a wider frequency band, than the "Zen 5c" cores. From what we can deduce from the current "Zen 4c" cores, "Zen 5c" cores aren't strictly "efficiency" cores, as they still offer the full breadth of core ISA as "Zen 5," including SMT. In its maximum configuration, "Strix Point" will hence be a 12-core/24-thread processor. The two CPU core types sit in two different CCX (CPU core complexes), the "Zen 5" CCX has 4 cores sharing a 16 MB L3 cache, while the "Zen 5c" CCX shares a 16 MB L3 cache among 8 cores. AMD will probably use a software-based solution to ensure the right kind of workload from the OS is processed by the right kind of CPU core.As for the integrated graphics, AMD is expected to deploy a large new iGPU based on the more advanced RDNA 3.5 graphics architecture, which has been referenced as "RDNA3+." It features 8 WGPs, or 16 CU, amounting to 1,024 stream processors, 64 TMUs, and an unknown number of ROPs (possibly 32), with the probable design goal of offering graphics performance close to a discrete Radeon RX 6500 XT graphics card. AMD will debut its second generation of the XDNA accelerator, the hardware backend of Ryzen AI. On "Strix Point," the accelerator is rumored to feature 64 AI Engines.
The chip's I/O is expected to be largely similar, with increase DDR5 memory speeds on offer—dual-channel (4x sub-channel) DDR5-5600 or LPDDR5X-8533, we don't know if AMD will update the PCIe interface to Gen 5 spec, the current "Phoenix" silicon is limited to Gen 4.
At this point, we don't know if "Strix Point" is a monolithic silicon, or a tiled processor, but AMD is expected to leverage the TSMC N4E (second gen 4 nm EUV) foundry node, for at least one of the tiles, or the whole die, in case this is a monolithic chip, with a total chip-area of around 225 mm².
Both core types feature an identical IPC, but the "Zen 5" cores can hold onto higher boost frequencies, and have a wider frequency band, than the "Zen 5c" cores. From what we can deduce from the current "Zen 4c" cores, "Zen 5c" cores aren't strictly "efficiency" cores, as they still offer the full breadth of core ISA as "Zen 5," including SMT. In its maximum configuration, "Strix Point" will hence be a 12-core/24-thread processor. The two CPU core types sit in two different CCX (CPU core complexes), the "Zen 5" CCX has 4 cores sharing a 16 MB L3 cache, while the "Zen 5c" CCX shares a 16 MB L3 cache among 8 cores. AMD will probably use a software-based solution to ensure the right kind of workload from the OS is processed by the right kind of CPU core.As for the integrated graphics, AMD is expected to deploy a large new iGPU based on the more advanced RDNA 3.5 graphics architecture, which has been referenced as "RDNA3+." It features 8 WGPs, or 16 CU, amounting to 1,024 stream processors, 64 TMUs, and an unknown number of ROPs (possibly 32), with the probable design goal of offering graphics performance close to a discrete Radeon RX 6500 XT graphics card. AMD will debut its second generation of the XDNA accelerator, the hardware backend of Ryzen AI. On "Strix Point," the accelerator is rumored to feature 64 AI Engines.
The chip's I/O is expected to be largely similar, with increase DDR5 memory speeds on offer—dual-channel (4x sub-channel) DDR5-5600 or LPDDR5X-8533, we don't know if AMD will update the PCIe interface to Gen 5 spec, the current "Phoenix" silicon is limited to Gen 4.
At this point, we don't know if "Strix Point" is a monolithic silicon, or a tiled processor, but AMD is expected to leverage the TSMC N4E (second gen 4 nm EUV) foundry node, for at least one of the tiles, or the whole die, in case this is a monolithic chip, with a total chip-area of around 225 mm².