Originally designed for the Pentium 2 platform, the AGP bus has undergone a multitude of evolutionary steps beginning with just AGP 1x (266MB\s) and ended with 8x (2.1GB\s) using the PCI specification as an operational baseline, the AGP specification adds 20 additional signals not included in the PCI bus.
The aim of the AGP bus is to provide a much smoother framerate and 3D rendered image in a much higher detail level than previously seen before on the PCI or ISA bus standards of old. The AGP bus is able to transfer high amounts of data due to it being able to transfer on both the rising and falling edges of the 66MHz bus clock frequency. AGP allows for direct data transfer between the graphics card and the CPU and \ or system memory. Although AGP is an extension of the PCI interface, it is completely (physically, logically and electrically) separate from the PCI bus. Therefore, activity of PCI peripherals won't affect the AGP card's performance.
AGP Technical Sheet:
Maximum transfer rates (32bit): 266MB\s (1x) 533MB\s (2x) 1066MB\s (4x) and 2100MB\s (8x)
Operating Frequency: 66MHz
Pipelined Requests
Address \ Data de-multiplexed
Single target, Single master
Memory Read \ Write only, no other I/O operations
High \ Low priority queues
Sideband Addressing
Fastwrites
Explanation of DIME
Direct Memory Execute (DIME) is probably the most important feature of the accelerated graphics port. AGP graphic chips have the capability to access main memory directly for the complex operation of texture mapping. AGP provides the graphics card with two methods of directly accessing texture maps in system memory: pipelining and sideband addressing. In pipelining, AGP makes multiple requests for data during a bus or memory access. Sideband addressing offers the highest level of AGP performance. In addition to allowing multiple outstanding transactions and non-coherent access to main memory, Sideband Addressing introduces a separate address \ command bus, the Sideband Address Port (SBA). Because the SBA and data buses are not multiplexed, the graphic controller can use the SBA to make data requests without interrupting the data bus.
During the lifetime of the AGP bus the port underwent a multitude of evolutionary steps forward as briefly mentioned earlier, here is a rundown of the revision history.
AGP 1.0 (1996) specification defined 1x and 2x speeds with the 3.3v keyed connector.
AGP 2.0 followed shortly after (1998), the specification defined 1x, 2x and 4x speeds with the 3.3v, or 1.5v keyed connector or a 'Universal' connector which supported both card types.
AGP Pro specification defined 1x, 2x and 4x speeds with the 3.3v, or 1.5v keyed connector or a 'Universal' connector which supported both card types.
The AGP 3.0 specification followed 4 years later (2002) and was the final evolutionary step in AGPs life, the specification defined 1x, 2x, 4x and 8x speeds with the 1.5v keyed connector, or a 1.5v AGP Universal / Pro connector. Each upgrade was a supper-set of the 1x mode, (4x would also support the 1x speed etc.) The base clock rate is 66MHz, but to achieve 2x, 4x, and 8x speeds the clock is doubled each time.
AGP (1x): 66MHz clock, 8 bytes/clock, Bandwidth: 266MB/s [3.3V or 1.5V signal swing]
AGP 2x: 133MHz clock, 8 bytes/clock, Bandwidth: 533MB/s [3.3V or 1.5V signal swing]
AGP 4x: 266MHz clock, 16 bytes/clock, Bandwidth: 1066MB/s [1.5V signal swing]
AGP 8x: 533MHz clock, 32 bytes/clock, Bandwidth: 2.1GB/s [0.8V signal swing], still uses 1.5 volt mainboard power.
The AGP data bus may be 8, 16, 24, 32, or 64 bits. Due to timing requirements the maximum bus length is 9". The trace impedance is specified as 65 ohms +/- 15 ohms (no termination resistor is specified). For the 8x speed the bus requires a parallel termination or 50 ohms. Some lines may require a Pull-Up Resistor to insure the lines come out of reset in the proper state.