Intel "Panther Lake" Confirmed on 18A Node, Powering-On With ES0 Silicon Revision

[AleksandarK]

During Barclays 22nd Annual Global Technology Conference, Intel was a guest and two of the interim company co-CEOs Michelle Johnston Holthaus and David Zinsner gave a little update on the state of affairs at Intel. One of the most interesting aspects of the talk was Intel's upcoming "Panther Lake" processor—a direct successor to Intel Core Ultra 200S "Arrow Lake-H" mobile processors. The company confirmed that Panther Lake would utilize an Intel 18A node and that a few select customers have powered on Panther Lake on the E0 engineering sample chip. "Now we are using Intel Foundry for Panther Lake, which is our 2025 product, which will land on 18A. And this is the first time that we're customer zero in a long time on an Intel process," said interim co-CEO Michelle Johnston Holthaus, adding, "But just to give some assurances, on Panther Lake, we have our ES0 samples out with customers. We have eight customers that have powered on, which gives you just kind of an idea that the health of the silicon is good and the health of the Foundry is good."

While we don't know what ES0 means for Intel internally, we can assume that it is one of the first engineering samples on the 18A. The "ES" moniker usually refers to engineering samples, and zero after it could be the first design iteration. For reference, Intel's "Panther Lake-H" will reportedly have up to 18 cores: 6 P-cores, 8 E-cores, and 4 LP cores. The design brings back low-power island E-cores in the SoC tile. The P-cores use "Cougar Cove," which should have a higher IPC than "Lion Cove," while keeping the existing "Skymont" E-cores. The SoC tile may move from Arrow Lake's 6 nm to a newer process to fit the LP cores and an updated NPU. The iGPU is said to use the Xe3 "Celestial" architecture. With Arrow Lake-H launching in early 2025, Panther Lake-H likely won't arrive until 2026.



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[LittleBro]

Last time there was information about chips on 18A (Panther Lake) are able to boot and power on (order of actions remains a mystery). Now they are able just to power on. Subtle difference.

The real question though is: Will it run Crysis?

EDIT: This is actually nothing new. Information regarding to chip powering on is nearly half year old.
Are they trolling investors? Michelle, for god's sake, get yourself synchronized, would ya?

 

[Bwaze]

What will Intel have as a backup plan, and release this in very limited run, like they did their 10nm fiasco, Cannon Lake in 2018?

 

[kondamin]

They need to be ready for market but samples just started?

 

[Wirko]

Last time there was information given about chips on 18A are able to boot. Not they are able to power on. Subtle difference.

If we suppose things are moving for the better, then the last time it booted without being powered on. This time it's capable of eating electricity and heating up as well. Hopefully it hasn't lost the ability to compute.

 

[londiste]

They need to be ready for market but samples just started?

Panther Lake is on roadmap for 25H2...

 

[kondamin]

Panther Lake is on roadmap for 25H2...

exactly, it's getting power and everything else still needs to be done including finding the bugs that's ++6months of work

 

[Daven]

Is there any way to tell if there would have been a physical difference between 20A and 18A? How do we know that 18A isn't just 20A so that Intel can claim they have a smaller number than the competition? Why would they do this? Because they are very late and want to match TSMC 2 nm releases.

 

[persondb]

Last time there was information about chips on 18A (Panther Lake) are able to boot and power on (order of actions remains a mystery). Now they are able just to power on. Subtle difference.

The real question though is: Will it run Crysis?

EDIT: This is actually nothing new. Information regarding to chip powering on is nearly half year old.
Are they trolling investors? Michelle, for god's sake, get yourself synchronized, would ya?

No, there is a pretty big difference. This is an Engineering Sample that is in Customer hands and it's working. It's not in Intel labs where they can apply any number of hacks to get it booting. It's news because it's part of the process of getting those CPU shipped, as those OEM customers are now working in products with those pre-production CPUs and any issue they have will likely result in another stepping of it.

 

[LittleBro]

No, there is a pretty big difference. This is an Engineering Sample that is in Customer hands and it's working. It's not in Intel labs where they can apply any number of hacks to get it booting. It's news because it's part of the process of getting those CPU shipped, as those OEM customers are now working in products with those pre-production CPUs and any issue they have will likely result in another stepping of it.

So that piece of silicon that Patsinger was holding in his hand was not even ES? Are you kidding me? ES are made way before (even 12 months) mass production. There are lots of samples.

We know only that it powers on and boots in customers machines. There's a loooooong time ahead, I see launch somewhere in Q3/24 at best.

 

[truerock]

IMHO...

Low power cores are good for notebook PCs where battery power is sometimes something people want - but, low-power cores cause desktop PCs to be less effective.

 

[truerock]

So that piece of silicon that Patsinger was holding in his hand was not even ES? Are you kidding me? ES are made way before (even 12 months) mass production. There are lots of samples.

We know only that it powers on and boots in customers machines. There's a loooooong time ahead, I see launch somewhere in Q3/24 at best.

Well, if someone was looking for something for him to hold on stage... I assume it was not a functional wafer. It's just a prop.

Engineering Sample -1?

 

[Nhonho]

Intel's "Panther Lake-H" will reportedly have up to 18 cores: 6 P-cores, 8 E-cores, and 4 LP cores.

Intel still uses this nonsense E cores... :facepalm:

For every 3 P cores, it should add 1 SP ("super core"), a brute force core, forming a set of 4 cores with 3 P cores + 1 SP (super core), since the software is (since forever) very poorly designed and practically always overloads 1 or 2 cores of the processor, even if it has dozens of cores. In this way, the software should be designed to overload the "super core" when it is very difficult or impossible to fragment the processing in the other cores.

 

[Darkmont]

Intel still uses this nonsense E cores... :facepalm:

For every 3 P cores, it should add 1 SP ("super core"), a brute force core, forming a set of 4 cores with 3 P cores + 1 SP (super core), since the software is (since forever) very poorly designed and practically always overloads 1 or 2 cores of the processor, even if it has dozens of cores. In this way, the software should be designed to overload the "super core" when it is very difficult or impossible to fragment the processing in the other cores.

The E-Cores have massively overperformed compared to the Haifa design team's Lion Cove. The "brute force" idea was killed when Royal Core died last year. One Lion Cove core fits where 3 E-Cores could be for only 10-20% more PPC.

 

[Wirko]

Intel still uses this nonsense E cores... :facepalm:

For every 3 P cores, it should add 1 SP ("super core"), a brute force core, forming a set of 4 cores with 3 P cores + 1 SP (super core), since the software is (since forever) very poorly designed and practically always overloads 1 or 2 cores of the processor, even if it has dozens of cores. In this way, the software should be designed to overload the "super core" when it is very difficult or impossible to fragment the processing in the other cores.

Hey, why not make every core different? We could have 8 cores called LP, Eminus, Ee, E, then P, P++, Pmaxpro, and finally SP. The scheduler would always know what load to put to each of them.

 

[Nhonho]

Hey, why not make every core different? We could have 8 cores called LP, Eminus, Ee, E, then P, P++, Pmaxpro, and finally SP. The scheduler would always know what load to put to each of them.

do what you want

 

[Squared]

Is there any way to tell if there would have been a physical difference between 20A and 18A? How do we know that 18A isn't just 20A so that Intel can claim they have a smaller number than the competition? Why would they do this? Because they are very late and want to match TSMC 2 nm releases.

I think 20A and 18A are a similar pattern to 4 and 3, where 3 featured high-densities libraries and lower leakage transistors which 4 did not. Panther Lake's CPU tile would probably be okay with 20A. But Intel's upcoming server chips and customer chips will really need the 18A features.

 

[qcmadness]

The E-Cores have massively overperformed compared to the Haifa design team's Lion Cove. The "brute force" idea was killed when Royal Core died last year. One Lion Cove core fits where 3 E-Cores could be for only 10-20% more PPC.

When you use Skymont as the main cores, the short comings of e-cores will be more visible.
In short, features of modern fast cores are not really present in Skymont.

 

[Nhonho]

They need to be ready for market but samples just started?

The sample is in the debug phase, which takes at least 1 year.

 

[londiste]

But Intel's upcoming server chips and customer chips will really need the 18A features.

I would say it is more about time to market rather than need or features. By the time they have customers wanting to produce on either of the nodes the 18A would already be up and running according to roadmap. If they are seeing 18A progressing well, it makes sense to just rush to that one. Switching over takes time and 20A was supposed to be a short-lived node. 18A is the last one in Gelsinger's 5 nodes in 4 years plan and should be a more persistent one in terms of lifetime. The whole reason for rushing through so many nodes in so little time is to catch up and if they can make 18A work in 2025 they are competitive with TSMC again.

Yes, that is an optimistic look or at least neutral take on Intel's statements. But not unrealistic.

 

[Wirko]

Is there any way to tell if there would have been a physical difference between 20A and 18A? How do we know that 18A isn't just 20A so that Intel can claim they have a smaller number than the competition? Why would they do this? Because they are very late and want to match TSMC 2 nm releases.

I think 20A and 18A are a similar pattern to 4 and 3, where 3 featured high-densities libraries and lower leakage transistors which 4 did not. Panther Lake's CPU tile would probably be okay with 20A. But Intel's upcoming server chips and customer chips will really need the 18A features.

Any conclusion here would be really muddy because we'd have to compare not two but three technologies: the optimistic 20A with PowerVia, the plan-B 20A Power Via missing, and the 18A.

Backside power delivery does increase density because the very crowded lowest metal layers don't have to carry power to every point. So the transistor layout may be better optimised without making transistors smaller. I think Intel mentioned a 5% improvement in density or so? And lower power loss too.

 

[londiste]

Backside power delivery should be primarily aimed at improving power efficiency. Density is a pretty secondary concern there.