Zen6 is almost here ?

[igormp]

DDR5 is first gen that we couldn't see 2x uplift in capacity, hence 24GiB and 48GiB modules.

FWIW, 64GB DDR5 UDIMMs are in retail since last month.

1. Quad channel (or better) RAM
2. Support for Registered ECC for really large amounts of memory
3. A significant increase in PCIe lanes

I believe you're correct in doubting those points, since they'd require way more pins, which would imply a new socket, so no way any of those will ever happen on AM5.

Arguably, already happened. DDR5 'split up' the existing dual channel architecture. Smaller/narrower channels clocked way higher, has gotten us to 3+ channel RAM, of generations gone by.

I really hate the "channel" terminology used for DIY x86 machines. Yeah, DDR5 has two "sub-channels", but a single DIMM is still 64-bit wide in data, and a "dual-channel" setup is still 128-bit, which is what limits bandwidth.
All the extra bandwidth comes from the higher clocks, which are not really directly caused by this "sub-channel" change.

Surprisingly, many AMD platforms have/have had 'unofficial' (unregistered-unbuffered) ECC support.
Also, 48GB DIMMs have helped.

I believe their point was more towards capacity than ECC itself, which requires RDIMMs.
But I agree, 48GB and the newest 64GB UDIMMs helped to mitigate the capacity issue at a reasonable price point.
128GB+ RDIMMs are hella expensive.

 

[Dr. Dro]

Why ? SMT doesn't cost zen that much. Only register pool is bigger than it would otherwise be (for register renaming etc).

In some new form it could be the new off-the-shelf high end.
Motherboards aren't that much more expensive and 8- or 10-layer PCB ain't so scary anymore.

Same with beefier I/O chiplet. Given how things are moving, 3Dcaching across the line is coming and multilayer 3D stacking is becoming the norm.
So all of that stuff that made ThreadRipper a monster is slowly trickling into new Ryzen 9s...

It's not about the cost, it's about performance and security implications. SMT technology belonged in low core count processors. Worthless these days, it's nothing but a cinebench score booster. Give me an extra 200-300 MHz over SMT on a modern 6+ core processor any day.

Anyway, it's not gonna be an off-the-shelf high-end, that was Threadripper up until TRX40, which got horribly aborted mid-way through its life and never even received a Zen 3 upgrade despite the fact that AMD fully developed it. They just chose to zip that market and favor EPYC in a time where there was extreme demand in the enterprise segment due to the lockdowns and prioritize that - smart financially, but screwed over HEDT buyers big time. Nowadays if you want these things, the entry cost for the Threadripper 7960X is $1500, plus a good chunk on a TRX80 motherboard, and of course, AMD is in no rush to update that platform to Zen 5.

I saw a nice ebay special the other day for a 5995WX (64 core) + 128GB ECC + Fancy Motherboard for under $4000.00. I was very tempted but I recently had an expensive car repair so it was a no go on that deal

That's a pretty good deal for that one, as long as the chip isn't vendor-locked. Shame you had to pass it up.

 

[igormp]

Worthless these days

Maybe if you're only thinking about games, but remember that the same Ryzen CCDs are also used in EPYCs, which do benefit quite well from SMT.

As long as those CCDs are mainly focused on making EPYC consumers happy, and are used in Ryzen CPUs as an afterthought, SMT will remain in place.

 

[Darby_Echo]

It's not about the cost, it's about performance and security implications. SMT technology belonged in low core count processors. Worthless these days, it's nothing but a cinebench score booster. Give me an extra 200-300 MHz over SMT on a modern 6+ core processor any day.

It works great on Linux. For code compiling and similar stuff it works very well. I suppose one could also craft a code that it would leverage it purposefully to even greater benefit.
One gets a way to use execution units that would otherwise idle. What's not to like ?

Anyway, it's not gonna be an off-the-shelf high-end, that was Threadripper up until TRX40, which got horribly aborted mid-way through its life and never even received a Zen 3 upgrade despite the fact that AMD fully developed it.

Well back then AMD had plenty of other things to worry about. HPC and AI weren't a thing back then also. AMD also wasn't ruling the top of the server world etc.

Now they are on top and the landscape is also different.
Since the frequency and IPC have plateoed, only way to go forward for now is core count, vector smartness and power.

For that, one needs more RAM and I/O bandwidth. Which means that something like TRX50 is to become new off-the-shelf high end, probably redefined to fit LP/CAMM2 or something similar.
And ThreadRipper world will be at 8-channel WRX90 and above.

 

[Sir Beregond]

3D cache on top and bottom

I believe it's pronounced menage a troi?

 

[Darby_Echo]

It's not about the cost, it's about performance and security implications. SMT technology belonged in low core count processors. Worthless these days, it's nothing but a cinebench score booster. Give me an extra 200-300 MHz over SMT on a modern 6+ core processor any day.

Anyway, it's not gonna be an off-the-shelf high-end, that was Threadripper up until TRX40, which got horribly aborted mid-way through its life and never even received a Zen 3 upgrade despite the fact that AMD fully developed it. They just chose to zip that market and favor EPYC in a time where there was extreme demand in the enterprise segment due to the lockdowns and prioritize that - smart financially, but screwed over HEDT buyers big time. Nowadays if you want these things, the entry cost for the Threadripper 7960X is $1500, plus a good chunk on a TRX80 motherboard, and of course, AMD is in no rush to update that platform to Zen 5.



That's a pretty good deal for that one, as long as the chip isn't vendor-locked. Shame you had to pass it up.

Not really that great. Here is new Zen4 ThreadRipper 64C/128T for a bit over €3k in EU:
AMD Ryzen Threadripper 7980X, 64C/128T, 3.20-5.10GHz, boxed

Nice boards for it for less than €1k:

 

[Dr. Dro]

Not really that great. Here is new Zen4 ThreadRipper 64C/128T for a bit over €3k in EU:
AMD Ryzen Threadripper 7980X, 64C/128T, 3.20-5.10GHz, boxed

Nice boards for it for less than €1k:

It's obviously on sale. The MSRP for this processor is $4,999 USD.

It works great on Linux. For code compiling and similar stuff it works very well. I suppose one could also craft a code that it would leverage it purposefully to even greater benefit.
One gets a way to use execution units that would otherwise idle. What's not to like ?

Well back then AMD had plenty of other things to worry about. HPC and AI weren't a thing back then also. AMD also wasn't ruling the top of the server world etc.

Now they are on top and the landscape is also different.
Since the frequency and IPC have plateoed, only way to go forward for now is core count, vector smartness and power.

For that, one needs more RAM and I/O bandwidth. Which means that something like TRX50 is to become new off-the-shelf high end, probably redefined to fit LP/CAMM2 or something similar.
And ThreadRipper world will be at 8-channel WRX90 and above.

Security hardened Linux distros actually disable SMT even if you don't toggle it off in the BIOS. Also I get the feeling you don't seem to understand how SMT works, it's not a matter of idleness but rather, a stalled pipeline. Except that you can perfectly offload that onto another core these days, it helped when cores were a luxury and not in abundance as they are today. Wouldn't count on CAMM being widely available just yet, btw.

Maybe if you're only thinking about games, but remember that the same Ryzen CCDs are also used in EPYCs, which do benefit quite well from SMT.

As long as those CCDs are mainly focused on making EPYC consumers happy, and are used in Ryzen CPUs as an afterthought, SMT will remain in place.

No, not only games. U9 285K's done away with it already and I don't expect this to come back for series 300, I reckon AMD's only kept it because they still have the 8 core CCD thing to worry about.

 

[mkppo]

In my opinion, AMD should follow Intel and remove SMT altogether from the next generation architecture. Make them dual CCD 12 cores with 12 threads each side. Much better, CPUs will be snappier, run cooler and won't have that side channel open all the time.

If you look at Zen 5, it's apparent that not only does SMT increase performance significantly for them but it's an inherent part of the arch with the dual decode engines etc. Mike Clark has an interview with chips and cheese, worth a watch.

They've also confirmed SMT is definitely in their plans moving forward, I wouldn't expect otherwise.

 

[Darby_Echo]

It's obviously on sale. The MSRP for this processor is $4,999 USD.



Security hardened Linux distros actually disable SMT even if you don't toggle it off in the BIOS. Also I get the feeling you don't seem to understand how SMT works, it's not a matter of idleness but rather, a stalled pipeline. Except that you can perfectly offload that onto another core these days, it helped when cores were a luxury and not in abundance as they are today. Wouldn't count on CAMM being widely available just yet, btw.

That doesn't mean it's useless.
Works great for me.

 

[qxp]

If you look at Zen 5, it's apparent that not only does SMT increase performance significantly for them but it's an inherent part of the arch with the dual decode engines etc. Mike Clark has an interview with chips and cheese, worth a watch.

They've also confirmed SMT is definitely in their plans moving forward, I wouldn't expect otherwise.

Modern CPUs are large enough and complex enough that it can be hard to say what "core" is, the same way how GPU compute units have ten different names referring to different ways of partitioning electronic circuit.

CPUs typically have the decode unit you mentioned that converts input instructions into microcode - microinstructions - that are executed by internal pipeline. This pipeline is commonly capable of having several microinstructions in flight that use different parts of hardware - load/store, ALU, multipliers, etc.

So now you have a problem of figuring out what core is - it a decode engine a core ? With hyperthreading enabled you typically decode more than pipeline can process to make the most of available hardware, so it seems like decode engine is slightly less than a core. What about execution pipeline ? It can process several instructions, so maybe it is more than a core.

And then what about multiplier units? On Xeons it is common to have 16-40 "Intel" cores and only 2 AVX-512 units. So if you are interested in 512-bit operations they only have two cores! (EDIT: Intel ARK is misleading, it is two AVX-512 units per core for Platinum and Gold Xeons, or one per hyperthread).

And if your program is memory bound then your "cores" are memory channels. The more the better, which is where multi-cpu configurations help. For example, a fairly recent Threadripper 7975WX has bandwidth of 240 GB/s and TDP of 350W, while quite old system of 2x Xeon Gold 6148 has aggregate memory bandwidth of 240 GB/s as well and TDP of 300W (CPUs alone). Move to newer CPUs and if you are not doing dual socket you are losing performance.

 

[Dr. Dro]

Modern CPUs are large enough and complex enough that it can be hard to say what "core" is, the same way how GPU compute units have ten different names referring to different ways of partitioning electronic circuit.

CPUs typically have the decode unit you mentioned that converts input instructions into microcode - microinstructions - that are executed by internal pipeline. This pipeline is commonly capable of having several microinstructions in flight that use different parts of hardware - load/store, ALU, multipliers, etc.

So now you have a problem of figuring out what core is - it a decode engine a core ? With hyperthreading enabled you typically decode more than pipeline can process to make the most of available hardware, so it seems like decode engine is slightly less than a core. What about execution pipeline ? It can process several instructions, so maybe it is more than a core.

And then what about multiplier units? On Xeons it is common to have 16-40 "Intel" cores and only 2 AVX-512 units. So if you are interested in 512-bit operations they only have two cores!

And if your program is memory bound then your "cores" are memory channels. The more the better, which is where multi-cpu configurations help. For example, a fairly recent Threadripper 7975WX has bandwidth of 240 GB/s and TDP of 350W, while quite old system of 2x Xeon Gold 6148 has aggregate memory bandwidth of 240 GB/s as well and TDP of 300W (CPUs alone). Move to newer CPUs and if you are not doing dual socket you are losing performance.

Only question I have, I believe the number of AVX-512 FMA units listed on Intel ARK for Xeon Scalable/Xeon 6 is per core, not chip wide?

 

[HD64G]

12-core chiplets and new IO is almost sure for Zen6. Problem is when it will arrive. I cannot see those CPUs on sale this year. Too early.

 

[Hyderz]

12-core chiplets and new IO is almost sure for Zen6. Problem is when it will arrive. I cannot see those CPUs on sale this year. Too early.

I’d predict July next year?

 

[Princess Garnet]

It makes no sense to disable half the CCD. maybe with just SMT removed 12/12.

Sorry, I may have typed that poorly.

I wasn't insinuating anything about disabling half the CCD. That was meant to read "Zen 6 and 12 CCD chips" so I'll edit it.

 

[qxp]

Only question I have, I believe the number of AVX-512 FMA units listed on Intel ARK for Xeon Scalable/Xeon 6 is per core, not chip wide?

I looked up and you are right. I always thought ARK listed total, because the list the total number of cores above. Thanks !

 

[lexluthermiester]

Next stop is CUDIMM support.

No thanks.

 

[HD64G]

I’d predict July next year?

My feeling is maybe 1-2 months earlier with an announcement in early 2026.

 

[A Computer Guy]

12-core chiplets and new IO is almost sure for Zen6. Problem is when it will arrive. I cannot see those CPUs on sale this year. Too early.

I can imagine AMD might do something weird like have a model with a 8 core chiplet with x3d cache + 12-core chiplet (maybe Zen6c) almost like a BIG.little type CPU.

 

[HD64G]

I can imagine AMD might do something weird like have a model with a 8 core chiplet with x3d cache + 12-core chiplet (maybe Zen6c) almost like a BIG.little type CPU.

12-core chiplets of Zen6 will be the full core ones, not the more efficient "c" ones. They are already making 12-core chiplets with the latter type of core for servers since Zen4.

 

[Wirko]

Speculation is a cornerstone of modern CPU design.
Without it, we wouldn't need Spectre mitigations.

Well said, sir. We're basically designing micro-processors at this stage, in this thread. I, for one, want to speculate about an AI branch predictor that's only wrong twice a day. Also, 3D cache on at least three floors, which includes L2 too. Also, 3- or 4-way HT with thread prioritisation. Then also some sort of mesh interconnect or another topology because the ring bus will become insufficient. I already mentioned an user-programmable FPGA, didn't I?

 

[A Computer Guy]

Well said, sir. We're basically designing micro-processors at this stage, in this thread. I, for one, want to speculate about an AI branch predictor that's only wrong twice a day. Also, 3D cache on at least three floors, which includes L2 too. Also, 3- or 4-way HT with thread prioritisation. Then also some sort of mesh interconnect or another topology because the ring bus will become insufficient. I already mentioned an user-programmable FPGA, didn't I?

Maybe an FPGA chiplet would be nice to have and the AI portion of the CPU could reprogram it depending on what you ask the CPU to do.

 

[R-T-B]

IIRC it was meant to have PCIe5 link, but ASSmedia lived to its name and screwed it up.

Isn't it literally just a reused X570 promontory, or am I misremembering?

No thanks.

Sir, I don't think we are driving the bus.

 

[R0H1T]

Make them dual CCD 12 cores with 12 threads each side. Much better, CPUs will be snappier, run cooler and won't have that side channel open all the time.

Side channel has little to do with SMT/HT besides all these attacks were also possible with Intel chips when they had HT disabled, it's a function/feature of OoO execution.

 

[lexluthermiester]

Isn't it literally just a reused X570 promontory, or am I misremembering?

Um, sure?

Sir, I don't think we are driving the bus.

No, but when the public gives input those that make the bus routes, listen and often change. The same principle applies.

However, I was mistakenly thinking of the CAMM crap. CUDIMM is something perfectly acceptable.

 

[R-T-B]

CUDIMM is something perfectly acceptable.

Agreed. Nothing wrong with faster dimms!

CAMM needs to stay in laptop land.