PCI-SIG Releases PCIe 7.0 Specification to Support 128.0 GT/s Transfer Rates

[TheDeeGee]

Make a better power connector, we don't need Gen7 for 20 years.

 

[lexluthermiester]

Don't get me wrong folks, I'm all for advancements and progress. However, let's utilize and optimize what we already have before we create two or three successors...

 

[tsunami2311]

and here i am with 3.0x16 system still and nvidia trying pawn off budget cards with a limited x8 that will basicly knee cap he card from 32gb/s to16gb/s, which reason I look at amd now and we dont even have 6.0 board yet,

 

[lexluthermiester]

and here i am with 3.0x16 system still and nvidia trying pawn off budget cards with a limited x8 that will basicly knee cap he card from 32gb/s to16gb/s, which reason I look at amd now and we dont even have 6.0 board yet,

Can we please not bring that nonsense into this thread?

 

[AsRock]

Maybe then we'll start getting those tiny STX motherboards with a PCIe 7.0 GPU slot edge connector. The traces will be nice and short for great signal integrity.


They'll find some way for AI to use it. You'll get a PCIe 7.0 M.2 for ultra fast local AI storage.

I have no reason to follow PCI-e any longer, going let ever sucker over pay for it until i need it. O yeah M.2 PCI5 HOT ?, OMG PCI-e 7 requires?, aah it's done to grind more money out of people is all.

 

[windwhirl]

From what I saw a while back, this just means we at the consumer level might see something with PCIE 7.0 in two or three years, not sooner.

 

[igormp]

Don't get me wrong folks, I'm all for advancements and progress. However, let's utilize and optimize what we already have before we create two or three successors...

I get what you mean, but this isn't really meant for consumers in any way. PCIe 5.0 is not really relevant for 95% of mainstream consumers, but it is a hell of a bottleneck for many enterprise applications.
Issue with PCIe 6.0 is that the PCIe-SIG has delayed their conformity program a lot, so there's no way for manufacturers to have 6.0 devices out there. As an example, Nvidia's DC Blackwell offerings already do support PCIe 6.0 since last year, but there's no way to make proper use of it without the remaining of the platform passing the conformity tests.

Let's hope that PCIe 7.0 does not face such bottlenecks.

For mainstream consumers this is pretty moot and 4.0 is enough for the majority of people. Heck, even 3.0 is good enough for almost all folks that just want to play games and don't do much else with their PCs.

 

[TumbleGeorge]

From what I saw a while back, this just means we at the consumer level might see something with PCIE 7.0 in two or three years, not sooner.

Do you read my comment with link to interview with SMI SEO from Anton Shilov that is in Tom's article? For the PCIe 6.0 SSD release date. You may hope PCIe 7.0 models to be on market before models on PCIe 6.0?

 

[windwhirl]

Do you read my comment with link to interview with SMI SEO from Anton Shilov that is in Tom's article? For the PCIe 6.0 SSD release date. You may hope PCIe 7.0 models to be on market before models on PCIe 6.0?

I was talking in general, not about a specific product

 

[TumbleGeorge]

I was talking in general, not about a specific product

No way to see something on PCIe 7.0 for ordinary consumers any soon or never. If it does happen, it will be in 10 years at the earliest.

 

[Random_User]

Spoiler

I'm still on 3.0

Heck, I'm still using PCIE 2.0, and SATA II as well

Enterprise market is really demanding faster interconnects, see NVLink and UALink, as well as new products on top of CXL being a thing now.

The cadence for new PCIe revisions has been shortening over time.
- 4.0 had its preliminary spec in 2011, final spec in 2017, and first products making use of it in 2017~2018.
- 5.0 had its preliminary spec in 2017, final spec in 2019, and the first devices in 2020.
- 6.0 had its preliminary spec in 2020, final spec in 2022, and the first devices are finally appearing this year. Blackwell in theory is PCIe 6.0 capable, but afaik the certification for that is not available yet.
- 7.0 had its preliminary spec in 2024, and we're seeing the final spec now, so I assume we will only be seeing devices on top of it by 2027 or so.

Enterprise adoption for 6.0 should happen plenty fast once the certifications are finally available, and hopefully 7.0 shouldn't take as long to become a thing.

Not to mention, the newer the scecs/PCIE Gen are faster to make and implement, due to the more of advanced tech is available. Thus accelerating the development and creation of next gen HW and standards.
Previous gen PCIE stuff was designed with comparably ancient tools with less specialists and tools involved. Though, the main principle and idea haven't changed much, it still was much slower and lenghtier process overall.

 

[Rightness_1]

All this messing around with expensive designs and signal integrity problems, power issues... All we need is a Fibre cable.

 

[The Von Matrices]

Not to mention, the newer the scecs/PCIE Gen are faster to make and implement, due to the more of advanced tech is available. Thus accelerating the development and creation of next gen HW and standards.
Previous gen PCIE stuff was designed with comparably ancient tools with less specialists and tools involved. Though, the main principle and idea haven't changed much, it still was much slower and lenghtier process overall.

It's easier to create specifications than to implement them. Sure, the specifications are designed with at least a little consideration of what is actually able to be implemented, but a not insignificant portion of technical specifications are the "cart leading the horse" using technology that is technically possible but impractical at the moment.

And it is getting harder to achieve these new specifications without tradeoffs like high power consumption or cost. PCIe v1 signals are able to stretch across an entire motherboard passively using cheap copper traces. But every subsequent generation has reduced the maximum trace length. Now to get the same distance with PCIe v6/v7, you need multiple expensive, power-hungry retransmitters or an exotic solutions like optical fiber--both of which are expensive. Just look at modern consumer platforms. They have a mix of PCIe v5, v4, and v3 to save cost rather than 100% PCIe v5. Back when PCIe v2/v3 was the newest tech, the entire platform was updated to use the newest spec.

 

[lexluthermiester]

All this messing around with expensive designs and signal integrity problems, power issues... All we need is a Fibre cable.

So optronics for the win? I'd go along with that.

 

[Rightness_1]

It's easier to create specifications than to implement them. Sure, the specifications are designed with at least a little consideration of what is actually able to be implemented, but a not insignificant portion of technical specifications are the "cart leading the horse" using technology that is technically possible but impractical at the moment.

And it is getting harder to achieve these new specifications without tradeoffs like high power consumption or cost. PCIe v1 signals are able to stretch across an entire motherboard passively using cheap copper traces. But every subsequent generation has reduced the maximum trace length. Now to get the same distance with PCIe v6/v7, you need multiple expensive, power-hungry retransmitters or an exotic solutions like optical fiber--both of which are expensive. Just look at modern consumer platforms. They have a mix of PCIe v5, v4, and v3 to save cost rather than 100% PCIe v5. Back when PCIe v2/v3 was the newest tech, the entire platform was updated to use the newest spec.

Yep PCIe is a mess.

 

[Prima.Vera]

Will the PCIe-7 SSD drives require L2H or L2N cooling, I wonder...

 

[LabRat 891]

Will the PCIe-7 SSD drives require L2H or L2N cooling, I wonder...

I wouldn't be surprised if we see either
A. a 'standard' for M.2 coolers or
B. E.1S (and its coolers) coming to desktop.

As-is, we've already seen benefit from liquid cooling Gen5 SSDs... kinda nuts.

 

[Random_User]

It's easier to create specifications than to implement them. Sure, the specifications are designed with at least a little consideration of what is actually able to be implemented, but a not insignificant portion of technical specifications are the "cart leading the horse" using technology that is technically possible but impractical at the moment.

And it is getting harder to achieve these new specifications without tradeoffs like high power consumption or cost. PCIe v1 signals are able to stretch across an entire motherboard passively using cheap copper traces. But every subsequent generation has reduced the maximum trace length. Now to get the same distance with PCIe v6/v7, you need multiple expensive, power-hungry retransmitters or an exotic solutions like optical fiber--both of which are expensive. Just look at modern consumer platforms. They have a mix of PCIe v5, v4, and v3 to save cost rather than 100% PCIe v5. Back when PCIe v2/v3 was the newest tech, the entire platform was updated to use the newest spec.

And it's 100% enterprise/datacenter oriented. For the HW, that operates petabytes+ of data, and requires colossal amount of bandwith and throughput. And with all these issues, stemmed from/caused by the nature of copper wiring, it's indeed more reasonable, to invest onto the fiber/optics development, instead.

And the consumer grade HW, should be left with lowed PCIE gens like 4.0-5.0/5.1 (due to unnecessary cost rise), up until the fiber becomes accessible and ironed out by enterprise market.

 

[chrcoluk]

In 10 years we will have pcie gen 10, but motherboards will cost 3000 USD for all the PCB layers.