Intel "Nova Lake‑S" Series: Seven SKUs, Up to 52 Cores and 150 W TDP

[AleksandarK]

Rumors of Intel's "Nova Lake-S" processors are increasing, meaning that the design is nearing completion. Expected to arrive in the second half of 2026, Nova Lake‑S will offer configurations ranging from mainstream quad‑core models to a flagship with 52 cores. Initial information suggests that Intel will employ a tile-based design, separating LPE cores from P-Cores and E-Cores to optimize flexibility and yield. At the top of the lineup is the rumored Core Ultra 9 model, possibly designated 385K. It will combine 16 P-cores, 32 E-cores, and four LPE-cores for a total of 52 cores, as previously rumored. With a TDP of 150 W, it will be the most powerful SKU Intel prepared for this generation. Below the flagship, Intel appears to be planning a Core Ultra 7 SKU with 14 P-cores, 24 E-cores, and four LPE cores, totaling 42 cores.

The Core Ultra 5 series may include three variants: a 28-core version with eight P-cores, 16 E-cores, and four LPE-cores; a 24-core version with eight P-cores, 12 E-cores, and four LPE-cores; and an 18-core model with six P-cores, eight E-cores, and four LPE-cores. Entry-level Core Ultra 3 parts would feature either a 16-core configuration with four P-cores, eight E-cores, and four LPE-cores, or a 12-core option with four P-cores, four E-cores, and four LPE-cores, both targeting a 65 W power envelope. All desktop SKUs are expected to feature four LPE cores on a separate die, suggesting a multi-tile package similar to Meteor Lake. Power demands will range from 65 W in entry-level segments to 150 W for high-end parts. Intel is reportedly preparing a new LGA 1954 socket even as it readies an Arrow Lake-S refresh for late 2025. Intel has also reportedly designated Xe3 "Celestial" for graphics rendering and Xe4 "Druid" for media and display duties.



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[Dr. Dro]

Can't wait to see how AMD will respond. If this holds these CPUs will be monsters.

 

[Daven]

So many big releases in 2026 on brand new fab nodes:

Nova Lake - up to 52 cores on 18A
Zen 6 - up to 48 or 64 threads on N2
UDNA - merging all GPU IP into one on N2
Rubin - more performance over blackwell on N2

 

[ThomasK]

Intel's PR material will definitely look good with all those cores.

Whether that translates into effective performance, however, is an entirely different story.

 

[Essaudio]

What’s the source of the rumors ?

 

[Chaitanya]

"150W"

 

[napata]

PBP is not TDP. It's just wrong to call it that. Intel hasn't used TDP terminology for years.

"150W"

For base clocks with a power virus workload which makes it total nonsense.

 

[dismuter]

This should be a significant generational leap in multi-threaded performance. Not sure about single threaded though, but hopefully they get much closer to Apple's M chips which have been humiliating everyone else on that front lately (not just x86, but also Qualcomm).

 

[halcyon]

Can't wait for both Intel and AMD to lag again, by keeping Nova Lake and Zen6 at DDR5 dual channel (probably 8800MT/s max), giving users a real world bandwidth of c. 120 GB/s max.

That's all fine and dandy for most basic tasks and even gaming, but computing in general, not just "AI" is becoming more and more memory/bandwidth bound and limited.

Apple has been giving consumers 260-380GB/s for the past two years. Now M4 Max is up to 500 GB/s. Guesstimates for M5 Max (going head to head with the above) are in the 500 to 700 GB/s range. Yes, I'm comparing SoCs to CPUs accessing RAM via DIMMs, but the AMD Ryzen AI+ Max 395 is equally bad and it's an integrated design.

Yes, design cycles are long in the tooth, but AMD and Intel should finally, after years of lagging, get with the RAM bandwidth program.

I'm getting bored waiting for something that offers 256GB RAM (and it works!) at good latencies, speeds and great bandwidth, without paying $60000+ for it.

But I expect Intel to fail this one with 99.999% probability, again. And I'm hopefully not the only one who thinks that dual channel DIMMs on a 52-core CPU is not necessarily the best idea ever.

 

[dgianstefani]

Can't wait for both Intel and AMD to lag again, by keeping Nova Lake and Zen6 at DDR5 dual channel (probably 8800MT/s max), giving users a real world bandwidth of c. 120 GB/s max.

That's all fine and dandy for most basic tasks and even gaming, but computing in general, not just "AI" is becoming more and more memory/bandwidth bound and limited.

Apple has been giving consumers 260-380GB/s for the past two years. Now M4 Max is up to 500 GB/s. Guesstimates for M5 Max (going head to head with the above) are in the 500 to 700 GB/s range. Yes, I'm comparing SoCs to CPUs accessing RAM via DIMMs, but the AMD Ryzen AI+ Max 395 is equally bad and it's an integrated design.

Yes, design cycles are long in the tooth, but AMD and Intel should finally, after years of lagging, get with the RAM bandwidth program.

I'm getting bored waiting for something that offers 256GB RAM (and it works!) at good latencies, speeds and great bandwidth, without paying $60000+ for it.

But I expect Intel to fail this one with 99.999% probability, again. And I'm hopefully not the only one who thinks that dual channel DIMMs on a 52-core CPU is not necessarily the best idea ever.

Current Intel chips can do 8800 MT+ with CUDIMM. New modules can do 10000+, I doubt the next gen won't have any improvements over Arrow Lake.

Furthermore, M4/M5 Max are extremely expensive chips, the systems they're in are many times the cost of a ~$700 top end consumer chip from Intel. There's the quad/octa channel chips/platforms for comparable prices.

 

[N/A]

8+16 used to be Ultra 9, now together with 6+8, 8+12 is advertised as ultra 5. Wildly different species.

 

[dgianstefani]

8+16 used to be Ultra 9, now together with 6+8, 8+12 is advertised as ultra 5. Wildly different species.

Quad cores used to be $600 parts, now they're available in pentium/celeron sub $100.

Natural evolution of P/E and node shrink is more cores, especially with HT deprecated for security/ST.

I think this is a great thing personally, only downside is having to buy more cores to get the best frequency bins. Kinda sucks if you only want/need ~20 threads as fast as possible etc.

 

[BArms]

Can't wait to see how AMD will respond. If this holds these CPUs will be monsters.

Ugh. I just want another 8p+0e SKU that runs at ~60C with a $35 cooler like my current 7800X3D. For the overwhelming vast majority of desktop PC users/gamers, 8P cores is the sweet spot, as most games still today don't use more than 1 or 2 cores anyway so after even 4 and especially 8 cores there are drastic diminishing returns for actual performance for real-world apps/games, these "52 cores" are great for rendering projects but complete overkill in the wrong direction for the vast majority of users Intel seems to be targeting.

I'd love to be wrong, maybe 2025 we'll finally get game engines and apps that can actually use all these cores but it seems unlikely.

 

[dgianstefani]

Ugh. I just want another 8p+0e SKU that runs at ~60C with a $35 cooler like my current 7800X3D. For the overwhelming vast majority of desktop PC users/gamers, 8P cores is the sweet spot, as most games still today don't use more than 1 or 2 cores anyway so after even 4 and especially 8 cores there are drastic diminishing returns for actual performance for real-world apps/games, these "52 cores" are great for rendering projects but complete overkill in the wrong direction for the vast majority of users Intel seems to be targeting.

I'd love to be wrong, maybe 2025 we'll finally get game engines and apps that can actually use all these cores but it seems unlikely.

The 32 e cores will take space of eight P. So for same die area they could have made 24+0+4, or gone with 16+32+4 P/E/LPE. I know which I'd pick. Hopefully cache is based off newer designs where it's e/p/e/p instead of PPP/eee etc, so can share LLC, so if you really care you can turn off E and P get more cache. But I really don't think it will make significant difference. If you want power budget to be spent on P cores all you have to do is clock e at iso efficiency, so like 3.2 GHz instead of stock 4.5 and you free up a lot of budget. Doesn't affect normal app perf since it's background tasks pinned to them anyway.

 

[dismuter]

Current Intel chips can do 8800 MT+ with CUDIMM. New modules can do 10000+, I doubt the next gen won't have any improvements over Arrow Lake.

Furthermore, M4/M5 Max are extremely expensive chips, the systems they're in are many times the cost of a ~$700 top end consumer chip from Intel. There's the quad/octa channel chips/platforms for comparable prices.

That RAM is unobtainium, and you won't find 10k MT/s any time soon at a reasonable price.
But even if we did, stretching so far would still only would reach 160 GB/s. It's a significant step up from 96 GB/s with DDR5-6000, but still much less than the 273 GB/s of the M4 Pro.
They need to either move to quad-channel or make a new DIMM format that is 128-bit.

 

[dgianstefani]

That RAM is unobtainium, and you won't find 10k MT/s any time soon at a reasonable price.
But even if we did, stretching so far would still only would reach 160 GB/s. It's a significant step up from 96 GB/s with DDR5-6000, but still much less than the 273 GB/s of the M4 Pro.
They need to either move to quad-channel or make a new DIMM format that is 128-bit.

It's called CAMM2 memory or any of the other new standards. So far only Intel supports CUDIMMs, the Strix Halo chip which doesn't make much sense to me also uses soldered in non DIMM format.

DIMMs are dead at these frequencies anyway. And true quad channel will not happen on consumer. Will either be single slot CAMM2 with whatever bandwidth they want and no physical slots/channels etc, or just soldered.

 

[JustBenching]

Can't wait to see how AMD will respond. If this holds these CPUs will be monsters.

With yet another 6core chip for 300$

 

[Onasi]

I'd love to be wrong, maybe 2025 we'll finally get game engines and apps that can actually use all these cores but it seems unlikely.

It’s unlikely for a rather simple reason - game logic is VERY hard to parallelize. It’s just inherently less scalable than many other workloads that these many-core chips are actually being built for. There’s a reason why more cache helps significantly more than more cores.

 

[chodaboy19]

Ugh. I just want another 8p+0e SKU that runs at ~60C with a $35 cooler like my current 7800X3D. For the overwhelming vast majority of desktop PC users/gamers, 8P cores is the sweet spot, as most games still today don't use more than 1 or 2 cores anyway so after even 4 and especially 8 cores there are drastic diminishing returns for actual performance for real-world apps/games, these "52 cores" are great for rendering projects but complete overkill in the wrong direction for the vast majority of users Intel seems to be targeting.

I'd love to be wrong, maybe 2025 we'll finally get game engines and apps that can actually use all these cores but it seems unlikely.

It's coming... eventually.

 

[qcmadness]

Current Intel chips can do 8800 MT+ with CUDIMM. New modules can do 10000+, I doubt the next gen won't have any improvements over Arrow Lake.

Furthermore, M4/M5 Max are extremely expensive chips, the systems they're in are many times the cost of a ~$700 top end consumer chip from Intel. There's the quad/octa channel chips/platforms for comparable prices.

High memory bandwidth does not automatically translate to high performance.

 

[dismuter]

Will either be single slot CAMM2 with whatever bandwidth they want

Whatever bandwidth they want? You mean clock speed?

Single slot means 128-bit max, the same as current DIMMs in dual channel configuration. That's not enough.

 

[LastDudeALive]

Intel's PR material will definitely look good with all those cores.

Whether that translates into effective performance, however, is an entirely different story.

The Core Ultra 9 285k matched the Zen 5 9950X in fully multi-threaded workloads with an 8 thread deficit (24 vs 32). So yeah, it will translate.

Apple has been giving consumers 260-380GB/s for the past two years. Now M4 Max is up to 500 GB/s. Guesstimates for M5 Max (going head to head with the above) are in the 500 to 700 GB/s range. Yes, I'm comparing SoCs to CPUs accessing RAM via DIMMs, but the AMD Ryzen AI+ Max 395 is equally bad and it's an integrated design.

Apple only makes chips that are going to have soldered RAM, so they can push the bandwidth as high as they can with RAM speed and bus width. As you said, comparing SoCs to CPUs that have to work in sockets is stupid, and for the AI Max chips, it's just not worth it for AMD to invent an entirely new memory controller just to give one specific product more bandwidth.

Also, the base M4 only gets 120GB/s with LPDDR5X 7500 MT/s. The higher bandwidth you're talking about is the fused chips, which is misleading and can't be replicated by Intel or AMD in consumer chips, especially when they want to sell for $200.

these "52 cores" are great for rendering projects but complete overkill in the wrong direction for the vast majority of users Intel seems to be targeting.

The 52 cores are going to be in the $600 CPU, The vast majority of users are not going to be buying it anyway. The mid-range chips have a reasonable 6-8 P cores, 8-12 e cores, and a LP island.

 

[dgianstefani]

High memory bandwidth does not automatically translate to high performance.

And? My post was replying to someone asking for quad channel DIMM on consumer desktop, since more cores need more bandwidth to stay fed. The point is you aren't going to see it, especially not combined with DIMM form factor. Market is moving to CAMM2/soldered.

 

[ThomasK]

So yeah, it will translate.

Those are your claims only. I'd much rather wait for actual reviews, than put my bets on some random guy's comments.

Also, I'm talking about general performance here, not the very niche and few workloads that actually fully utilize Intel's P and E cores. Most users don't need or will benefit from all those extra E-cores, hence why it's more of a PR gimmick than anything else.

Lastly, please do blindly trust Intel's judgment of how many cores the average user needs, but don't forget it is the same company that gave you nothing but 4-cores on 7 generations of products.

 

[dgianstefani]

Whatever bandwidth they want? You mean clock speed?

Single slot means 128-bit max, the same as current DIMMs in dual channel configuration. That's not enough.

No, I mean what I wrote, whatever bandwidth they want, whether that's from clock or channels or both. I still think it's wishful thinking to desire quad slots each feeding a channel on consumer motherboards. At best, we might see dual slot CAMM2, for quad channel, but I suspect we will instead see MT scale well past 10000.

Again, if you want memory bandwidth, you don't go to a consumer platform, and again, the M4 Max you're comparing to is a significantly more expensive platform than the upcoming Intel Nova Lake, and the actual competition in the x86 space is from workstation platforms.

JEDEC Publishes New CAMM2 Memory Module Standard

JEDEC Solid State Technology Association, the global leader in the development of standards for the microelectronics industry, today announced the publication of JESD318: Compression Attached Memory Module (CAMM2) Common Standard. This groundbreaking standard defines the electrical and...

www.techpowerup.com

This scalability from single-channel and dual-channel configurations to future multi-channel setups promises a significant boost in memory capacity.