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AMD X499 Chipset Alive, Could See CES 2019 Unveil

btarunr

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AMD is going ahead with its plans to launch a new HEDT platform chipset dubbed X499, according to a HD Technologia report. Originally rumored to launch alongside the 2nd Generation Ryzen Threadripper family, X499 was delayed indefinitely, and the current X399 chipset continued as AMD's premier HEDT chipset, with existing motherboards receiving BIOS updates to support 2nd Gen Threadrippers, and some motherboard manufacturers launching newer models with beefed up CPU VRM designs to better cope with the 24-core and 32-core Threadrippers.

AMD X499 is reportedly back on the company's roadmap, and slated for a CES 2019 unveiling (January). What's interesting here is AMD sticking to the model number "499" after it emerged that Intel's next HEDT chipset could be named "X599." There's no information on what X499 brings to the table, but there are two big areas for improvement: first, the downstream PCI-Express connectivity needs to be updated to current PCI-Express gen 3.0 standards; and second, unless Threadripper WX processors are hardwired to only support quad-channel memory; X499 could introduce 8-channel memory, which could make it even more competitive against Intel's upcoming 28-core HEDT processor that has 6-channel memory.



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Well, let's see if they unlock octa-channel memory on Threadripper. That is potentially the biggest point of X499.

My bet is that they won't. Because doing so will effectively kill off all Naples EPYCs and mid-tier Rome EPYCs. Allowing prosumer producs to disrupt enteprise market is a desperate move, like what Intel is doing. AMD is neither so altruistic nor desperate.
 
Consumers frankly don't need more than quad channel. Besides, why would they ruin their own market with it...
 
Well, let's see if they unlock octa-channel memory on Threadripper. That is potentially the biggest point of X499.

My bet is that they won't. Because doing so will effectively kill off all Naples EPYCs and mid-tier Rome EPYCs. Allowing prosumer producs to disrupt enteprise market is a desperate move, like what Intel is doing. AMD is neither so altruistic nor desperate.
That's not gonna happen, what would be the point of EPYC then :rolleyes:

What could happen with Zen 2 & Zen3 is higher speed mem support, even for TR. If you've had a look at most TR reviews, including a handful that show 2970x numbers, you'll notice that TR isn't always bandwidth starved. The 2 dies not connected directly with memory is what kills it's performance, so 8 core per CCX is the next logical move IMO.
 
Why would the chipset have anything to do with the amount of memory channels available?

Sure, new X499 based boards might support additional memory channels, but there's no way a new chipset would have anything to do with it.
 
Why would the chipset have anything to do with the amount of memory channels available?

Sure, new X499 based boards might support additional memory channels, but there's no way a new chipset would have anything to do with it.

the X399 chipset has design concepts AMD have dictated, instead of bringing in a shitstorm of confusion that this x399 supports 8 channel but not this one they don't.
X499 may have a switch to change between 8 and 4 channel memory but I wonder about trace length if such a device is used as the dram wires are hard wired to cpu's today and matter extremely much on higher memory frequencies.
 
I hope everyone reading TPU are aware that the memory controller is inside the CPU these days and have been for many, many years.

So again, I ask, why would the chipset have anything to do with memory channels?
 
I hope everyone reading TPU are aware that the memory controller is inside the CPU these days and have been for many, many years.

So again, I ask, why would the chipset have anything to do with memory channels?
Nothing other than allowing for new board designs which could add such function if the CPUs were capable (which they should not be, but who knows, since AMD said they'd never release 4-die TR chips for X399, yet did anyway a year later).
 
I hope everyone reading TPU are aware that the memory controller is inside the CPU these days and have been for many, many years.

So again, I ask, why would the chipset have anything to do with memory channels?

AMD makes X399.
These pins go to dimm XY, you pair two slots to one channel but it's optional.
This is the PCI-E Lane configuration.
They should support this power budget as a minimum.

Once AMD makes X499 they can make new demands to board layouts, in that way it changes how everything is, X489 could be a 2 channel board and same chipset but it's rules that come with the chipset platform which is how Intel and AMD uses chipsets nowadays.

There is also electrical wiring for 4-> 8 channel memory and mixing those on same chipset name is not a lucky situation so how do you solve it?
New chipset as a platform upgrade and say 8 channel memory as a feature upgrade with the chipset cause it's easier, more organized way of doing it.

Chipsets matter, mostly as a platform specification and not as the chipset itself.
 
AMD makes X399.
These pins go to dimm XY, you pair two slots to one channel but it's optional.
This is the PCI-E Lane configuration.
They should support this power budget as a minimum.

Once AMD makes X499 they can make new demands to board layouts, in that way it changes how everything is, X489 could be a 2 channel board and same chipset but it's rules that come with the chipset platform which is how Intel and AMD uses chipsets nowadays.

There is also electrical wiring for 4-> 8 channel memory and mixing those on same chipset name is not a lucky situation so how do you solve it?
New chipset as a platform upgrade and say 8 channel memory as a feature upgrade with the chipset cause it's easier, more organized way of doing it.

Chipsets matter, mostly as a platform specification and not as the chipset itself.

Actually, no, ASMedia makes the chipsets for AMD these days.

Again, why would any pins whatsoever go from the chipset to the DIMM slots?

Sure, I never said they wouldn't allow new board designs with a new chipset, this is pretty much the norm, no?

Yes, sure, but from the CPU socket, not the chipset.
 
I think the best thing amd can do is connect one channel of each die to a channel of the motherboard, I do not think they have limitations unless there are several CPU pins that have no connections with memory slots.

By the way, this is my first post. XD
 
@Eselmio makes a good point and that would help reduce cannibalisation of Epyc too as you wouldn't get the capacity/dual channel controller per RAM channel.

What would be nice, even without the RAM, would be if they hooked up even one more set of PCIe lanes. Bringing it to 96 lanes would still be less than Epyc and require much less wiring changes than adding even one more memory channel - they could do 6 channel too which would be an interesting middle ground.

With 96 PCIe lanes, you;d have 4 x full 16 and still have 16 extra to play with. What about putting another 4 x Ultra M.2 on the back side of the motherboard for example or like ASUS on a dedicated slot.

Things like uncontended 2 x 10GBe or indeed an on-board Thunderbolt stuck in the same way as the WiFi modules are done etc.

As mentioned, all of this assumes the 2nd two dice have the pins connected.

This would also mean we'd need the lower SKUs to have the full 4 dice in the package, but maybe they could use dies that only have the PCIe complex and/or RAM controller working for the 2nd two and thus use up otherwise useless dice. That would be quite cool.
 
Consumers frankly don't need more than quad channel. Besides, why would they ruin their own market with it...

You forget the term power user

Sounds like you beg the question
 
I've had triple and quad channel long before it became anywhere near "mainstream" and frankly, what really matters is still RAM capacity and not RAM speed or width. Lack of RAM makes everything basically stall. Where channels and speed just slightly change the performance metrics on the higher end. Which means, unless you're using really crappy slow RAM in dual channel, there isn't much difference even for so called "power users".
 
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