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TSMC Claims Breakthrough on 1nm Chip Production

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TSMC in collaboration with the National Taiwan University (NTU) and the Massachusetts Institute of Technology (MIT) have made a significant breakthrough in the development of 1-nanometer chips. The joint announcement comes after IBM earlier this month published news of their 2-nanometer chip development. The researchers found that the use of semi-metal bismuth (Bi) as contact electrodes for the 2D matrix can greatly reduce resistance and increase current. This discovery was first made by the MIT team before then being further refined by TSMC and NTU which will increase energy efficiency and performance in future processors. The 1-nanometer node won't be deployed for several years with TSMC planning to start 3-nanometer production in H2 2022.



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Wow! The barriers keep dropping.
 
!

How is that even a thing?
 
This discovery was first made by the MIT team before then being further refined by TSMC and NUT which will increase energy efficiency and performance in future processors.
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Haha small but funny spelling mistake. I believe the NUT in the 2nd last sentence should be NTU.

Thanks for the article! gives hope for the future of semiconductors.
 
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There is a physical limit to how small a process can go before the constraints of the manufacturing equipment and atomic density prevents further reduction. 1nm is getting really close to that limit..
 
JohnWal said:
So true and a comment probably lost on most posters....
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While I agree that it's slightly dishonest, one can argue that it started to matter a whole lot less when the state of the art switched (hehe geddit) away from planar transistors.
Putting 'nm numbers' on things like FinFETs, GAA FETs and whatever else they're cooking up doesn't really make all that much sense anymore anyway, and as technologies continue to develop it's less and less about those nanometers.

If only there was something else both straightforward and catchy that can represent both performance and scaling of the most basic building blocks of transistors these days,..

Edit: It makes me think of those oldskool "3200+" names AMD put on their CPUs when clocks started to matter less compared to IPC. It's not really a straightforward metaphor but similar imho.
 
JohnWal said:
Dammeron said:
Probably true 8nm or so...
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So true and a comment probably lost on most posters....
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The scaling factor has been superseded by the current drive which is the main factor that made FinFET so dominant.
Prior to FinFET, 3D gates weren't present. Actual 3D gates in the shape of GAAFET and MBCFET are 4D in comparison since the gate is surrounding the source in 4 directions instead of 3.
 
Mathragh said:
Demand drives price,... Let's hope by that time supply is better able to serve it :)
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While true on economic papers, scalpers and bots drives prices ;)
 
mechtech said:
While true on economic papers, scalpers and bots drives prices ;)
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I agree that they currently do have an influence on prices, but would they also be able to do the same if there was enough supply to satisfy demand?
If anything it says to me that the products are too cheap for their demand so people are capitalizing on the difference. If supply and demand were in balance, scalpers shouldn't have a chance.
 
Ravenas said:
pm
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"My GPU has 1 PM!! How do I respond to it????"

In all seriousness, I wonder what this means for CPUs and GPUs. Will this drive safe voltages down, up, or something else?
 
RealKGB said:
"My GPU has 1 PM!! How do I respond to it????"

In all seriousness, I wonder what this means for CPUs and GPUs. Will this drive safe voltages down, up, or something else?
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Speaking broadly on top end hardware, all die shrinks have done so far is drive hz up and power up.
 
matar said:
0.1 nm after that the end...lol
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Just for the record, a single Si atom's atomic radius is slightly larger than 0.1nm, which puts its diameter at approximately 0.2nm. I would love to hear how they'd make a transistor gate smaller than a silicon atom. :p
 
The next major step is how to do 3d stacking (2d slices stacked), then 3d chips.

In both case, the major issue will be the cooling. This is why 3d stacking is targeted right now at low power devices. But all manufacturer are working on solutions for that.
 
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